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dd53274771
This reverts commit 80a34ae31125aa46dcad47162ba45b152aed968d with fixes. Previously, since bots turning on EXPENSIVE_CHECKS are essentially turning on MachineVerifierPass by default on X86 and the fact that inline-asm-avx-v-constraint-32bit.ll and inline-asm-avx512vl-v-constraint-32bit.ll are not expected to generate functioning machine code, this would go down to `report_fatal_error` in MachineVerifierPass. Here passing `-verify-machineinstrs=0` to make the intent explicit.
28 lines
1004 B
TableGen
28 lines
1004 B
TableGen
// RUN: not --crash llvm-tblgen -gen-dag-isel -I %p/../../include %s 2>&1 | FileCheck %s
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// The HwModeSelect class is intended to serve as a base class for other
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// classes that are then used to select a value based on the HW mode.
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// It contains a list of HW modes, and a derived class should provide a
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// list of corresponding values.
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// These two lists must have the same size. Make sure that a violation of
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// this requirement is diagnosed.
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include "llvm/Target/Target.td"
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def TestTargetInstrInfo : InstrInfo;
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def TestTarget : Target {
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let InstructionSet = TestTargetInstrInfo;
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}
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def TestReg : Register<"testreg">;
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def TestClass : RegisterClass<"TestTarget", [i32], 32, (add TestReg)>;
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def TestMode1 : HwMode<"+feat1">;
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def TestMode2 : HwMode<"+feat2">;
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def BadDef : ValueTypeByHwMode<[TestMode1, TestMode2, DefaultMode],
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[i8, i16, i32, i64]>;
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// CHECK: error: in record BadDef derived from HwModeSelect: the lists Modes and Objects should have the same size
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