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0983c108c8
Summary: MIPSR6 introduces a class of branches called compact branches. Unlike the traditional MIPS branches which have a delay slot, compact branches do not have a delay slot. The instruction following the compact branch is only executed if the branch is not taken and must not be a branch. It works by generating compact branches for MIPS32R6 when the delay slot filler cannot fill a delay slot. Then, inspecting the generated code for forbidden slot hazards (a compact branch with an adjacent branch or other CTI) and inserting nops to clear this hazard. Patch by Simon Dardis. Reviewers: vkalintiris, dsanders Subscribers: MatzeB, dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D16353 llvm-svn: 263444
193 lines
6.3 KiB
LLVM
193 lines
6.3 KiB
LLVM
; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefix=ALL -check-prefix=FCC -check-prefix=32-FCC
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; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=ALL -check-prefix=FCC -check-prefix=32-FCC
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; RUN: llc < %s -march=mipsel -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL -check-prefix=GPR -check-prefix=32-GPR
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; RUN: llc < %s -march=mips64el -mcpu=mips64 | FileCheck %s -check-prefix=ALL -check-prefix=FCC -check-prefix=64-FCC
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; RUN: llc < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL -check-prefix=FCC -check-prefix=64-FCC
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; RUN: llc < %s -march=mips64el -mcpu=mips64r6 | FileCheck %s -check-prefix=ALL -check-prefix=GPR -check-prefix=64-GPR
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define void @func0(float %f2, float %f3) nounwind {
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entry:
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; ALL-LABEL: func0:
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; 32-FCC: c.eq.s $f12, $f14
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; 64-FCC: c.eq.s $f12, $f13
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; FCC: bc1f $BB0_2
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; 32-GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $f14
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; 64-GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $f13
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; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
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; FIXME: We ought to be able to transform not+bnez -> beqz
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; GPR: not $[[GPRCC]], $[[GPRCC]]
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; 32-GPR: bnez $[[GPRCC]], $BB0_2
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; 64-GPR: bnezc $[[GPRCC]], $BB0_2
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%cmp = fcmp oeq float %f2, %f3
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br i1 %cmp, label %if.then, label %if.else
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if.then: ; preds = %entry
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tail call void (...) @g0() nounwind
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br label %if.end
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if.else: ; preds = %entry
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tail call void (...) @g1() nounwind
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br label %if.end
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if.end: ; preds = %if.else, %if.then
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ret void
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}
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declare void @g0(...)
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declare void @g1(...)
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define void @func1(float %f2, float %f3) nounwind {
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entry:
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; ALL-LABEL: func1:
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; 32-FCC: c.olt.s $f12, $f14
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; 64-FCC: c.olt.s $f12, $f13
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; FCC: bc1f $BB1_2
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; 32-GPR: cmp.ule.s $[[FGRCC:f[0-9]+]], $f14, $f12
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; 64-GPR: cmp.ule.s $[[FGRCC:f[0-9]+]], $f13, $f12
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; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
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; GPR-NOT: not $[[GPRCC]], $[[GPRCC]]
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; 32-GPR: bnez $[[GPRCC]], $BB1_2
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; 64-GPR: bnezc $[[GPRCC]], $BB1_2
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%cmp = fcmp olt float %f2, %f3
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br i1 %cmp, label %if.then, label %if.else
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if.then: ; preds = %entry
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tail call void (...) @g0() nounwind
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br label %if.end
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if.else: ; preds = %entry
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tail call void (...) @g1() nounwind
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br label %if.end
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if.end: ; preds = %if.else, %if.then
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ret void
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}
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define void @func2(float %f2, float %f3) nounwind {
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entry:
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; ALL-LABEL: func2:
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; 32-FCC: c.ole.s $f12, $f14
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; 64-FCC: c.ole.s $f12, $f13
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; FCC: bc1t $BB2_2
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; 32-GPR: cmp.ult.s $[[FGRCC:f[0-9]+]], $f14, $f12
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; 64-GPR: cmp.ult.s $[[FGRCC:f[0-9]+]], $f13, $f12
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; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
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; GPR-NOT: not $[[GPRCC]], $[[GPRCC]]
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; 32-GPR: beqz $[[GPRCC]], $BB2_2
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; 64-GPR: beqzc $[[GPRCC]], $BB2_2
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%cmp = fcmp ugt float %f2, %f3
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br i1 %cmp, label %if.else, label %if.then
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if.then: ; preds = %entry
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tail call void (...) @g0() nounwind
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br label %if.end
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if.else: ; preds = %entry
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tail call void (...) @g1() nounwind
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br label %if.end
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if.end: ; preds = %if.else, %if.then
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ret void
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}
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define void @func3(double %f2, double %f3) nounwind {
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entry:
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; ALL-LABEL: func3:
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; 32-FCC: c.eq.d $f12, $f14
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; 64-FCC: c.eq.d $f12, $f13
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; FCC: bc1f $BB3_2
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; 32-GPR: cmp.eq.d $[[FGRCC:f[0-9]+]], $f12, $f14
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; 64-GPR: cmp.eq.d $[[FGRCC:f[0-9]+]], $f12, $f13
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; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
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; FIXME: We ought to be able to transform not+bnez -> beqz
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; GPR: not $[[GPRCC]], $[[GPRCC]]
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; 32-GPR: bnez $[[GPRCC]], $BB3_2
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; 64-GPR: bnezc $[[GPRCC]], $BB3_2
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%cmp = fcmp oeq double %f2, %f3
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br i1 %cmp, label %if.then, label %if.else
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if.then: ; preds = %entry
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tail call void (...) @g0() nounwind
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br label %if.end
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if.else: ; preds = %entry
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tail call void (...) @g1() nounwind
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br label %if.end
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if.end: ; preds = %if.else, %if.then
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ret void
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}
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define void @func4(double %f2, double %f3) nounwind {
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entry:
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; ALL-LABEL: func4:
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; 32-FCC: c.olt.d $f12, $f14
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; 64-FCC: c.olt.d $f12, $f13
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; FCC: bc1f $BB4_2
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; 32-GPR: cmp.ule.d $[[FGRCC:f[0-9]+]], $f14, $f12
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; 64-GPR: cmp.ule.d $[[FGRCC:f[0-9]+]], $f13, $f12
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; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
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; GPR-NOT: not $[[GPRCC]], $[[GPRCC]]
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; 32-GPR: bnez $[[GPRCC]], $BB4_2
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; 64-GPR: bnezc $[[GPRCC]], $BB4_2
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%cmp = fcmp olt double %f2, %f3
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br i1 %cmp, label %if.then, label %if.else
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if.then: ; preds = %entry
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tail call void (...) @g0() nounwind
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br label %if.end
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if.else: ; preds = %entry
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tail call void (...) @g1() nounwind
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br label %if.end
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if.end: ; preds = %if.else, %if.then
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ret void
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}
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define void @func5(double %f2, double %f3) nounwind {
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entry:
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; ALL-LABEL: func5:
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; 32-FCC: c.ole.d $f12, $f14
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; 64-FCC: c.ole.d $f12, $f13
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; FCC: bc1t $BB5_2
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; 32-GPR: cmp.ult.d $[[FGRCC:f[0-9]+]], $f14, $f12
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; 64-GPR: cmp.ult.d $[[FGRCC:f[0-9]+]], $f13, $f12
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; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
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; GPR-NOT: not $[[GPRCC]], $[[GPRCC]]
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; 32-GPR: beqz $[[GPRCC]], $BB5_2
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; 64-GPR: beqzc $[[GPRCC]], $BB5_2
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%cmp = fcmp ugt double %f2, %f3
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br i1 %cmp, label %if.else, label %if.then
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if.then: ; preds = %entry
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tail call void (...) @g0() nounwind
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br label %if.end
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if.else: ; preds = %entry
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tail call void (...) @g1() nounwind
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br label %if.end
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if.end: ; preds = %if.else, %if.then
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ret void
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}
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