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c168815f4b
Summary: The -mcpu=mips16 option caused the Integrated Assembler to crash because it couldn't figure out the architecture revision number to write to the .MIPS.abiflags section. This CPU definition has been removed because, like microMIPS, MIPS16 is an ASE to a base architecture. Reviewers: vkalintiris Subscribers: rkotler, llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D13656 llvm-svn: 250407
115 lines
5.3 KiB
LLVM
115 lines
5.3 KiB
LLVM
; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___fixunsdfsi
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; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___floatdidf
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; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___floatdisf
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; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___floatundidf
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; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___fixsfdi
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; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___fixunsdfdi
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; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___fixdfdi
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; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___fixunssfsi
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; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___fixunssfdi
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; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___floatundisf
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@ll1 = global i64 0, align 8
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@ll2 = global i64 0, align 8
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@ll3 = global i64 0, align 8
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@l1 = global i32 0, align 4
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@l2 = global i32 0, align 4
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@l3 = global i32 0, align 4
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@ull1 = global i64 0, align 8
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@ull2 = global i64 0, align 8
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@ull3 = global i64 0, align 8
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@ul1 = global i32 0, align 4
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@ul2 = global i32 0, align 4
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@ul3 = global i32 0, align 4
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@d1 = global double 0.000000e+00, align 8
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@d2 = global double 0.000000e+00, align 8
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@d3 = global double 0.000000e+00, align 8
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@d4 = global double 0.000000e+00, align 8
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@f1 = global float 0.000000e+00, align 4
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@f2 = global float 0.000000e+00, align 4
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@f3 = global float 0.000000e+00, align 4
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@f4 = global float 0.000000e+00, align 4
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; Function Attrs: nounwind
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define void @_Z3foov() #0 {
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entry:
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%0 = load double, double* @d1, align 8
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%conv = fptosi double %0 to i64
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store i64 %conv, i64* @ll1, align 8
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%1 = load double, double* @d2, align 8
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%conv1 = fptoui double %1 to i64
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store i64 %conv1, i64* @ull1, align 8
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%2 = load float, float* @f1, align 4
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%conv2 = fptosi float %2 to i64
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store i64 %conv2, i64* @ll2, align 8
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%3 = load float, float* @f2, align 4
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%conv3 = fptoui float %3 to i64
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store i64 %conv3, i64* @ull2, align 8
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%4 = load double, double* @d3, align 8
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%conv4 = fptosi double %4 to i32
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store i32 %conv4, i32* @l1, align 4
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%5 = load double, double* @d4, align 8
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%conv5 = fptoui double %5 to i32
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store i32 %conv5, i32* @ul1, align 4
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%6 = load float, float* @f3, align 4
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%conv6 = fptosi float %6 to i32
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store i32 %conv6, i32* @l2, align 4
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%7 = load float, float* @f4, align 4
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%conv7 = fptoui float %7 to i32
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store i32 %conv7, i32* @ul2, align 4
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ret void
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}
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; Function Attrs: nounwind
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define void @_Z3goov() #0 {
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entry:
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%0 = load i64, i64* @ll1, align 8
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%conv = sitofp i64 %0 to double
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store double %conv, double* @d1, align 8
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%1 = load i64, i64* @ull1, align 8
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%conv1 = uitofp i64 %1 to double
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store double %conv1, double* @d2, align 8
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%2 = load i64, i64* @ll2, align 8
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%conv2 = sitofp i64 %2 to float
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store float %conv2, float* @f1, align 4
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%3 = load i64, i64* @ull2, align 8
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%conv3 = uitofp i64 %3 to float
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store float %conv3, float* @f2, align 4
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%4 = load i32, i32* @l1, align 4
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%conv4 = sitofp i32 %4 to double
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store double %conv4, double* @d3, align 8
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%5 = load i32, i32* @ul1, align 4
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%conv5 = uitofp i32 %5 to double
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store double %conv5, double* @d4, align 8
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%6 = load i32, i32* @l2, align 4
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%conv6 = sitofp i32 %6 to float
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store float %conv6, float* @f3, align 4
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%7 = load i32, i32* @ul2, align 4
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%conv7 = uitofp i32 %7 to float
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store float %conv7, float* @f4, align 4
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ret void
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}
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attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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; __call_stub_fp___fixunsdfsi: __call_stub_fp___fixunsdfsi:
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; __call_stub_fp___floatdidf: __call_stub_fp___floatdidf:
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; __call_stub_fp___floatdisf: __call_stub_fp___floatdisf:
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; __call_stub_fp___floatundidf: __call_stub_fp___floatundidf:
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; __call_stub_fp___fixsfdi: __call_stub_fp___fixsfdi:
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; __call_stub_fp___fixunsdfdi: __call_stub_fp___fixunsdfdi:
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; __call_stub_fp___fixdfdi: __call_stub_fp___fixdfdi:
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; __call_stub_fp___fixunssfsi: __call_stub_fp___fixunssfsi:
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; __call_stub_fp___fixunssfdi: __call_stub_fp___fixunssfdi:
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; __call_stub_fp___floatundisf: __call_stub_fp___floatundisf:
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