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f7a5afdf0a
Chapter 3 of the QPX manual states that, "Scalar floating-point load instructions, defined in the Power ISA, cause a replication of the source data across all elements of the target register." Thus, if we have a load followed by a QPX splat (from the first lane), the splat is redundant. This adds a late MI-level pass to remove the redundant splats in some of these cases (specifically when both occur in the same basic block). This optimization is scheduled just prior to post-RA scheduling. It can't happen before anything that might replace the load with some already-computed quantity (i.e. store-to-load forwarding). llvm-svn: 265047
49 lines
1.3 KiB
CMake
49 lines
1.3 KiB
CMake
set(LLVM_TARGET_DEFINITIONS PPC.td)
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tablegen(LLVM PPCGenAsmWriter.inc -gen-asm-writer)
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tablegen(LLVM PPCGenAsmMatcher.inc -gen-asm-matcher)
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tablegen(LLVM PPCGenDisassemblerTables.inc -gen-disassembler)
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tablegen(LLVM PPCGenMCCodeEmitter.inc -gen-emitter)
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tablegen(LLVM PPCGenRegisterInfo.inc -gen-register-info)
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tablegen(LLVM PPCGenInstrInfo.inc -gen-instr-info)
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tablegen(LLVM PPCGenDAGISel.inc -gen-dag-isel)
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tablegen(LLVM PPCGenFastISel.inc -gen-fast-isel)
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tablegen(LLVM PPCGenCallingConv.inc -gen-callingconv)
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tablegen(LLVM PPCGenSubtargetInfo.inc -gen-subtarget)
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add_public_tablegen_target(PowerPCCommonTableGen)
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add_llvm_target(PowerPCCodeGen
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PPCBoolRetToInt.cpp
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PPCAsmPrinter.cpp
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PPCBranchSelector.cpp
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PPCCTRLoops.cpp
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PPCHazardRecognizers.cpp
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PPCInstrInfo.cpp
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PPCISelDAGToDAG.cpp
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PPCISelLowering.cpp
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PPCEarlyReturn.cpp
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PPCFastISel.cpp
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PPCFrameLowering.cpp
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PPCLoopPreIncPrep.cpp
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PPCMCInstLower.cpp
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PPCMachineFunctionInfo.cpp
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PPCMIPeephole.cpp
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PPCRegisterInfo.cpp
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PPCQPXLoadSplat.cpp
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PPCSubtarget.cpp
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PPCTargetMachine.cpp
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PPCTargetObjectFile.cpp
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PPCTargetTransformInfo.cpp
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PPCTOCRegDeps.cpp
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PPCTLSDynamicCall.cpp
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PPCVSXCopy.cpp
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PPCVSXFMAMutate.cpp
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PPCVSXSwapRemoval.cpp
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)
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add_subdirectory(AsmParser)
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add_subdirectory(Disassembler)
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add_subdirectory(InstPrinter)
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add_subdirectory(TargetInfo)
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add_subdirectory(MCTargetDesc)
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