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0c6bc1e223
Previously, we would expand: %BL<def> = COPY %DL<kill>, %EBX<imp-use,kill>, %EBX<imp-def> Into: %BL<def> = MOV8rr %DL<kill>, %EBX<imp-def> Dropping the imp-use on the floor. That confused CriticalAntiDepBreaker, which (correctly) assumes that if an instruction defs but doesn't use a register, that register is dead immediately before the instruction - while in this case, the high lanes of EBX can be very much alive. This fixes PR28560. Differential Revision: https://reviews.llvm.org/D22425 llvm-svn: 275634
23 lines
751 B
LLVM
23 lines
751 B
LLVM
; Tests for the two-address instruction pass.
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; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a9 -arm-atomic-cfg-tidy=0 %s -o - | FileCheck %s
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define void @PR13378() nounwind {
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; This was orriginally a crasher trying to schedule the instructions.
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; CHECK-LABEL: PR13378:
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; CHECK: vld1.32
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; CHECK-NEXT: vmov.i32
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; CHECK-NEXT: vst1.32
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; CHECK-NEXT: vst1.32
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; CHECK-NEXT: vmov.f32
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; CHECK-NEXT: vmov.f32
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; CHECK-NEXT: vst1.32
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entry:
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%0 = load <4 x float>, <4 x float>* undef, align 4
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store <4 x float> zeroinitializer, <4 x float>* undef, align 4
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store <4 x float> %0, <4 x float>* undef, align 4
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%1 = insertelement <4 x float> %0, float 1.000000e+00, i32 3
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store <4 x float> %1, <4 x float>* undef, align 4
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unreachable
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}
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