Saleem Abdulrasool 63a10bee58 tests: tweak MIR for ARM tests to correct MI issues ... The Machine Instruction Verifier flagged some issues in the serialized MIR. Adjust the input to correct them. Fixes the remaining portion of PR27480. llvm-svn: 267578		2016-04-26 17:54:21 +00:00
..
AArch64	[AArch64] Expand v1i64 and v2i64 ctlz.	2016-04-26 05:26:51 +00:00
AMDGPU	[AMDGPU] Reserve VGPRs for trap handler usage if instructed	2016-04-26 15:43:14 +00:00
ARM	[ARM] Expand vector ctlz_zero_undef so it becomes ctlz.	2016-04-26 05:04:37 +00:00
BPF
CPP
Generic	Introduce llvm.load.relative intrinsic.	2016-04-22 21:18:02 +00:00
Hexagon	[Hexagon] Register save/restore functions do not follow regular conventions	2016-04-25 17:49:44 +00:00
Inputs
Lanai	[lanai] Add subword scheduling itineraries.	2016-04-20 18:28:55 +00:00
Mips	[mips][microMIPS] Revert commit r267137	2016-04-25 15:40:08 +00:00
MIR	tests: tweak MIR for ARM tests to correct MI issues	2016-04-26 17:54:21 +00:00
MSP430
NVPTX
PowerPC	[PowerPC] Add support for llvm.thread.pointer	2016-04-26 10:37:22 +00:00
SPARC	[SPARC] [SSP] Add support for LOAD_STACK_GUARD.	2016-04-26 10:37:14 +00:00
SystemZ	[SystemZ] [SSP] Add support for LOAD_STACK_GUARD.	2016-04-24 13:57:49 +00:00
Thumb
Thumb2
WebAssembly	[WebAssembly] Account for implicit operands when computing operand indices.	2016-04-26 01:40:56 +00:00
WinEH
X86	[CodeGenPrepare] use branch weight metadata to decide if a select should be turned into a branch	2016-04-26 17:11:17 +00:00
XCore