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llvm-mirror/test/CodeGen
Justin Lebar 63ae2eb95c [NVPTX] Enable the load-store vectorizer on nvptx.
Reviewers: tra

Subscribers: jholewinski, arsenm, asbirlea

Differential Revision: https://reviews.llvm.org/D22592

llvm-svn: 276196
2016-07-20 22:11:36 +00:00
..
AArch64 [AArch64][FastISel] Select -O0 legal cmpxchg. 2016-07-20 21:12:32 +00:00
AMDGPU GlobalISel: implement low-level type with just size & vector lanes. 2016-07-20 19:09:30 +00:00
ARM [ARM] Skip inline asm memory operands in DAGToDAGISel 2016-07-20 09:48:24 +00:00
BPF
Generic Move mempcpy_call.ll to X86 subdirectory 2016-07-13 18:28:45 +00:00
Hexagon [Hexagon] Handle returning small structures by value 2016-07-18 17:30:41 +00:00
Inputs
Lanai [lanai] Use peephole optimizer to generate more conditional ALU operations. 2016-07-07 23:36:04 +00:00
Mips Revert "RegScavenging: Add scavengeRegisterBackwards()" 2016-07-20 00:21:32 +00:00
MIR GlobalISel: implement low-level type with just size & vector lanes. 2016-07-20 19:09:30 +00:00
MSP430
NVPTX [NVPTX] Enable the load-store vectorizer on nvptx. 2016-07-20 22:11:36 +00:00
PowerPC Revert "RegScavenging: Add scavengeRegisterBackwards()" 2016-07-20 00:21:32 +00:00
SPARC VirtRegMap: Replace some identity copies with KILL instructions. 2016-07-09 00:19:07 +00:00
SystemZ Revert "RegScavenging: Add scavengeRegisterBackwards()" 2016-07-20 00:21:32 +00:00
Thumb Revert "RegScavenging: Add scavengeRegisterBackwards()" 2016-07-20 00:21:32 +00:00
Thumb2 [Thumb] Reapply r272251 with a fix for PR28348 (mk 2) 2016-07-05 12:37:13 +00:00
WebAssembly [WebAssembly] Emit type signatures for declared functions 2016-06-03 18:34:36 +00:00
WinEH revert http://reviews.llvm.org/D21101 2016-06-30 17:52:24 +00:00
X86 [X86][AVX512] Added AVX512 subvector broadcast tests 2016-07-19 17:04:28 +00:00
XCore IR: Introduce Module::global_objects(). 2016-06-22 20:29:42 +00:00