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b087bfb569
As discussed on D62910, we need to check whether particular types of memory access are allowed, not just their alignment/address-space. This NFC patch adds a MachineMemOperand::Flags argument to allowsMemoryAccess and allowsMisalignedMemoryAccesses, and wires up calls to pass the relevant flags to them. If people are happy with this approach I can then update X86TargetLowering::allowsMisalignedMemoryAccesses to handle misaligned NT load/stores. Differential Revision: https://reviews.llvm.org/D63075 llvm-svn: 363179
144 lines
6.2 KiB
C++
144 lines
6.2 KiB
C++
//===- MipsSEISelLowering.h - MipsSE DAG Lowering Interface -----*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// Subclass of MipsTargetLowering specialized for mips32/64.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H
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#define LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H
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#include "MipsISelLowering.h"
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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#include "llvm/Support/MachineValueType.h"
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namespace llvm {
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class MachineBasicBlock;
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class MachineInstr;
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class MipsSubtarget;
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class MipsTargetMachine;
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class SelectionDAG;
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class TargetRegisterClass;
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class MipsSETargetLowering : public MipsTargetLowering {
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public:
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explicit MipsSETargetLowering(const MipsTargetMachine &TM,
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const MipsSubtarget &STI);
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/// Enable MSA support for the given integer type and Register
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/// class.
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void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC);
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/// Enable MSA support for the given floating-point type and
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/// Register class.
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void addMSAFloatType(MVT::SimpleValueType Ty,
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const TargetRegisterClass *RC);
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bool allowsMisalignedMemoryAccesses(
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EVT VT, unsigned AS = 0, unsigned Align = 1,
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MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
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bool *Fast = nullptr) const override;
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
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MachineBasicBlock *
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EmitInstrWithCustomInserter(MachineInstr &MI,
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MachineBasicBlock *MBB) const override;
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bool isShuffleMaskLegal(ArrayRef<int> Mask, EVT VT) const override {
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return false;
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}
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const TargetRegisterClass *getRepRegClassFor(MVT VT) const override;
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private:
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bool isEligibleForTailCallOptimization(
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const CCState &CCInfo, unsigned NextStackOffset,
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const MipsFunctionInfo &FI) const override;
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void
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getOpndList(SmallVectorImpl<SDValue> &Ops,
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std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
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bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
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bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
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SDValue Chain) const override;
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SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerMulDiv(SDValue Op, unsigned NewOpc, bool HasLo, bool HasHi,
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SelectionDAG &DAG) const;
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SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
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/// Lower VECTOR_SHUFFLE into one of a number of instructions
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/// depending on the indices in the shuffle.
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SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
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MachineBasicBlock *emitBPOSGE32(MachineInstr &MI,
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MachineBasicBlock *BB) const;
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MachineBasicBlock *emitMSACBranchPseudo(MachineInstr &MI,
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MachineBasicBlock *BB,
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unsigned BranchOp) const;
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/// Emit the COPY_FW pseudo instruction
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MachineBasicBlock *emitCOPY_FW(MachineInstr &MI,
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MachineBasicBlock *BB) const;
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/// Emit the COPY_FD pseudo instruction
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MachineBasicBlock *emitCOPY_FD(MachineInstr &MI,
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MachineBasicBlock *BB) const;
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/// Emit the INSERT_FW pseudo instruction
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MachineBasicBlock *emitINSERT_FW(MachineInstr &MI,
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MachineBasicBlock *BB) const;
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/// Emit the INSERT_FD pseudo instruction
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MachineBasicBlock *emitINSERT_FD(MachineInstr &MI,
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MachineBasicBlock *BB) const;
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/// Emit the INSERT_([BHWD]|F[WD])_VIDX pseudo instruction
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MachineBasicBlock *emitINSERT_DF_VIDX(MachineInstr &MI,
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MachineBasicBlock *BB,
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unsigned EltSizeInBytes,
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bool IsFP) const;
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/// Emit the FILL_FW pseudo instruction
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MachineBasicBlock *emitFILL_FW(MachineInstr &MI,
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MachineBasicBlock *BB) const;
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/// Emit the FILL_FD pseudo instruction
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MachineBasicBlock *emitFILL_FD(MachineInstr &MI,
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MachineBasicBlock *BB) const;
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/// Emit the FEXP2_W_1 pseudo instructions.
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MachineBasicBlock *emitFEXP2_W_1(MachineInstr &MI,
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MachineBasicBlock *BB) const;
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/// Emit the FEXP2_D_1 pseudo instructions.
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MachineBasicBlock *emitFEXP2_D_1(MachineInstr &MI,
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MachineBasicBlock *BB) const;
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/// Emit the FILL_FW pseudo instruction
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MachineBasicBlock *emitLD_F16_PSEUDO(MachineInstr &MI,
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MachineBasicBlock *BB) const;
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/// Emit the FILL_FD pseudo instruction
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MachineBasicBlock *emitST_F16_PSEUDO(MachineInstr &MI,
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MachineBasicBlock *BB) const;
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/// Emit the FEXP2_W_1 pseudo instructions.
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MachineBasicBlock *emitFPEXTEND_PSEUDO(MachineInstr &MI,
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MachineBasicBlock *BB,
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bool IsFGR64) const;
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/// Emit the FEXP2_D_1 pseudo instructions.
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MachineBasicBlock *emitFPROUND_PSEUDO(MachineInstr &MI,
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MachineBasicBlock *BBi,
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bool IsFGR64) const;
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H
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