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b9148f5d85
Summary: Extend cachepolicy operand in the new VMEM buffer intrinsics to supply information whether the buffer data is swizzled. Also, propagate this information to MIR. Intrinsics updated: int_amdgcn_raw_buffer_load int_amdgcn_raw_buffer_load_format int_amdgcn_raw_buffer_store int_amdgcn_raw_buffer_store_format int_amdgcn_raw_tbuffer_load int_amdgcn_raw_tbuffer_store int_amdgcn_struct_buffer_load int_amdgcn_struct_buffer_load_format int_amdgcn_struct_buffer_store int_amdgcn_struct_buffer_store_format int_amdgcn_struct_tbuffer_load int_amdgcn_struct_tbuffer_store Furthermore, disable merging of VMEM buffer instructions in SI Load/Store optimizer, if the "swizzled" bit on the instruction is on. The default value of the bit is 0, meaning that data in buffer is linear and buffer instructions can be merged. There is no difference in the generated code with this commit. However, in the future it will be expected that front-ends use buffer intrinsics with correct "swizzled" bit set. Reviewers: arsenm, nhaehnle, tpr Reviewed By: nhaehnle Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, arphaman, jfb, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68200 llvm-svn: 373491
160 lines
6.6 KiB
YAML
160 lines
6.6 KiB
YAML
# RUN: llc -march=amdgcn -mcpu=gfx803 -run-pass si-memory-legalizer %s -o - | FileCheck %s
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--- |
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define amdgpu_kernel void @multiple_mem_operands(i32 addrspace(1)* %out, i32 %cond, i32 %if_offset, i32 %else_offset) #0 {
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entry:
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%scratch0 = alloca [8192 x i32], addrspace(5)
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%scratch1 = alloca [8192 x i32], addrspace(5)
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%scratchptr01 = bitcast [8192 x i32] addrspace(5)* %scratch0 to i32 addrspace(5)*
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store i32 1, i32 addrspace(5)* %scratchptr01
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%scratchptr12 = bitcast [8192 x i32] addrspace(5)* %scratch1 to i32 addrspace(5)*
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store i32 2, i32 addrspace(5)* %scratchptr12
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%cmp = icmp eq i32 %cond, 0
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br i1 %cmp, label %if, label %else, !structurizecfg.uniform !0, !amdgpu.uniform !0
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if: ; preds = %entry
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%if_ptr = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch0, i32 0, i32 %if_offset, !amdgpu.uniform !0
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%if_value = load i32, i32 addrspace(5)* %if_ptr, align 4, !nontemporal !1
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br label %done, !structurizecfg.uniform !0
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else: ; preds = %entry
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%else_ptr = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch1, i32 0, i32 %else_offset, !amdgpu.uniform !0
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%else_value = load i32, i32 addrspace(5)* %else_ptr, align 4, !nontemporal !1
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br label %done, !structurizecfg.uniform !0
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done: ; preds = %else, %if
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%value = phi i32 [ %if_value, %if ], [ %else_value, %else ]
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store i32 %value, i32 addrspace(1)* %out
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ret void
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}
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; Function Attrs: convergent nounwind
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declare { i1, i64 } @llvm.amdgcn.if(i1) #1
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; Function Attrs: convergent nounwind
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declare { i1, i64 } @llvm.amdgcn.else(i64) #1
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; Function Attrs: convergent nounwind readnone
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declare i64 @llvm.amdgcn.break(i64) #2
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; Function Attrs: convergent nounwind readnone
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declare i64 @llvm.amdgcn.if.break(i1, i64) #2
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; Function Attrs: convergent nounwind readnone
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declare i64 @llvm.amdgcn.else.break(i64, i64) #2
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; Function Attrs: convergent nounwind
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declare i1 @llvm.amdgcn.loop(i64) #1
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; Function Attrs: convergent nounwind
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declare void @llvm.amdgcn.end.cf(i64) #1
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attributes #0 = { "target-cpu"="gfx803" }
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attributes #1 = { convergent nounwind }
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attributes #2 = { convergent nounwind readnone }
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!0 = !{}
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!1 = !{i32 1}
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...
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---
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# CHECK-LABEL: name: multiple_mem_operands
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# CHECK-LABEL: bb.3.done:
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# CHECK: BUFFER_LOAD_DWORD_OFFEN killed $vgpr0, killed $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 0, 1, 1, 0, 0
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name: multiple_mem_operands
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alignment: 1
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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liveins:
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- { reg: '$sgpr0_sgpr1', virtual-reg: '' }
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- { reg: '$sgpr3', virtual-reg: '' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 65540
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offsetAdjustment: 0
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maxAlignment: 4
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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savePoint: ''
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restorePoint: ''
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fixedStack:
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- { id: 0, type: default, offset: 0, size: 4, alignment: 4, stack-id: default,
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isImmutable: false, isAliased: false, callee-saved-register: '' }
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stack:
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- { id: 0, name: scratch0, type: default, offset: 4, size: 32768, alignment: 4,
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stack-id: default, callee-saved-register: '', local-offset: 0,
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debug-info-variable: '', debug-info-expression: '',
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debug-info-location: '' }
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- { id: 1, name: scratch1, type: default, offset: 32772, size: 32768,
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alignment: 4, stack-id: default, callee-saved-register: '', local-offset: 32768,
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debug-info-variable: '', debug-info-expression: '',
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debug-info-location: '' }
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constants:
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body: |
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bb.0.entry:
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successors: %bb.1.if(0x30000000), %bb.2.else(0x50000000)
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liveins: $sgpr0_sgpr1, $sgpr3
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$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 44, 0, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(4)* undef`)
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$sgpr8 = S_MOV_B32 &SCRATCH_RSRC_DWORD0, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11
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$sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM $sgpr0_sgpr1, 36, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`)
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$sgpr9 = S_MOV_B32 &SCRATCH_RSRC_DWORD1, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11
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$sgpr10 = S_MOV_B32 4294967295, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11
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$sgpr11 = S_MOV_B32 15204352, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11
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$vgpr0 = V_MOV_B32_e32 1, implicit $exec
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BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 4, 0, 0, 0, 0, 0, implicit $exec :: (store 4 into %ir.scratchptr01)
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S_WAITCNT 127
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S_CMP_LG_U32 killed $sgpr2, 0, implicit-def $scc
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S_WAITCNT 3855
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$vgpr0 = V_MOV_B32_e32 2, implicit $exec
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$vgpr1 = V_MOV_B32_e32 32772, implicit $exec
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BUFFER_STORE_DWORD_OFFEN killed $vgpr0, killed $vgpr1, $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 4 into %ir.scratchptr12)
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S_CBRANCH_SCC0 %bb.1.if, implicit killed $scc
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bb.2.else:
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successors: %bb.3.done(0x80000000)
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liveins: $sgpr0_sgpr1, $sgpr4_sgpr5, $sgpr3, $sgpr8_sgpr9_sgpr10_sgpr11
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$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 52, 0, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(4)* undef`)
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S_WAITCNT 3855
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$vgpr0 = V_MOV_B32_e32 32772, implicit $exec
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S_BRANCH %bb.3.done
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bb.1.if:
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successors: %bb.3.done(0x80000000)
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liveins: $sgpr0_sgpr1, $sgpr4_sgpr5, $sgpr3, $sgpr8_sgpr9_sgpr10_sgpr11
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$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 48, 0, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(4)* undef`)
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S_WAITCNT 3855
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$vgpr0 = V_MOV_B32_e32 4, implicit $exec
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bb.3.done:
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liveins: $sgpr3, $sgpr4_sgpr5, $sgpr8_sgpr9_sgpr10_sgpr11, $vgpr0, $sgpr0
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S_WAITCNT 127
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$sgpr0 = S_LSHL_B32 killed $sgpr0, 2, implicit-def dead $scc
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$vgpr0 = V_ADD_I32_e32 killed $sgpr0, killed $vgpr0, implicit-def dead $vcc, implicit $exec
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$vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr0, killed $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 0, 0, 0, 0, 0, 0, implicit $exec :: (non-temporal load 4 from %ir.else_ptr), (non-temporal load 4 from %ir.if_ptr)
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$vgpr1 = V_MOV_B32_e32 $sgpr4, implicit $exec, implicit-def $vgpr1_vgpr2, implicit $sgpr4_sgpr5
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$vgpr2 = V_MOV_B32_e32 killed $sgpr5, implicit $exec, implicit $sgpr4_sgpr5, implicit $exec
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S_WAITCNT 3952
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FLAT_STORE_DWORD killed $vgpr1_vgpr2, killed $vgpr0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into %ir.out)
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S_ENDPGM 0
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...
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