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81d794ab6d
Remove FeatureSlowMisaligned128Store from cyclone flags. This flag causes splitting of 16 byte wide stores into 2 stored of 8 bytes. This was useful on older apple CPUs which were slow for 16byte stores that were not aligned on 16byte. As the compiler often cannot predict the actual alignment, the splitting was choosen. This has been a topic for a lot of debate as the splitting also decreases performance for some benchmarks. Measuring the effects on newer apple chips (rdar://35525421) shows that it harms more cases than it helps. So it is time to retire this workaround. llvm-svn: 323289
53 lines
2.1 KiB
LLVM
53 lines
2.1 KiB
LLVM
; RUN: llc < %s -mtriple=aarch64-unknown-unknown -mcpu=cyclone -mattr=+slow-misaligned-128store | FileCheck %s --check-prefix=SPLITTING --check-prefix=CHECK
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; RUN: llc < %s -mtriple=aarch64-eabi -mattr=-slow-misaligned-128store | FileCheck %s --check-prefix=MISALIGNED --check-prefix=CHECK
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@g0 = external global <3 x float>, align 16
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@g1 = external global <3 x float>, align 4
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; CHECK: ldr q[[R0:[0-9]+]], {{\[}}[[R1:x[0-9]+]], :lo12:g0
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; CHECK: str d[[R0]]
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define void @blam() {
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%tmp4 = getelementptr inbounds <3 x float>, <3 x float>* @g1, i64 0, i64 0
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%tmp5 = load <3 x float>, <3 x float>* @g0, align 16
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%tmp6 = extractelement <3 x float> %tmp5, i64 0
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store float %tmp6, float* %tmp4
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%tmp7 = getelementptr inbounds float, float* %tmp4, i64 1
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%tmp8 = load <3 x float>, <3 x float>* @g0, align 16
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%tmp9 = extractelement <3 x float> %tmp8, i64 1
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store float %tmp9, float* %tmp7
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ret void;
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}
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; PR21711 - Merge vector stores into wider vector stores.
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; On Cyclone, the stores should not get merged into a 16-byte store because
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; unaligned 16-byte stores are slow. This test would infinite loop when
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; the fastness of unaligned accesses was not specified correctly.
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define void @merge_vec_extract_stores(<4 x float> %v1, <2 x float>* %ptr) {
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%idx0 = getelementptr inbounds <2 x float>, <2 x float>* %ptr, i64 3
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%idx1 = getelementptr inbounds <2 x float>, <2 x float>* %ptr, i64 4
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%shuffle0 = shufflevector <4 x float> %v1, <4 x float> undef, <2 x i32> <i32 0, i32 1>
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%shuffle1 = shufflevector <4 x float> %v1, <4 x float> undef, <2 x i32> <i32 2, i32 3>
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store <2 x float> %shuffle0, <2 x float>* %idx0, align 8
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store <2 x float> %shuffle1, <2 x float>* %idx1, align 8
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ret void
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; MISALIGNED-LABEL: merge_vec_extract_stores
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; MISALIGNED: stur q0, [x0, #24]
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; MISALIGNED-NEXT: ret
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; FIXME: Ideally we would like to use a generic target for this test, but this relies
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; on suppressing store pairs.
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; SPLITTING-LABEL: merge_vec_extract_stores
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; SPLITTING: ext v1.16b, v0.16b, v0.16b, #8
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; SPLITTING-NEXT: str d0, [x0, #24]
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; SPLITTING-NEXT: str d1, [x0, #32]
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; SPLITTING-NEXT: ret
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}
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