Matt Arsenault 64c65e28b3 AMDGPU/GlobalISel: Use more wide vector load/stores ... This improves the type breakdown for some large vectors. For example, we now get a <4 x s32> and s32 store instead of 5 s32 stores for <5 x s32>.		2020-02-01 10:47:21 -05:00
..
AArch64	[AArch64][GlobalISel] Walk through G_TRUNC in getTestBitReg	2020-01-31 11:09:55 -08:00
AMDGPU	AMDGPU/GlobalISel: Use more wide vector load/stores	2020-02-01 10:47:21 -05:00
ARC
ARM	[GlobalISel] Tidy up unnecessary calls to createGenericVirtualRegister	2020-01-31 17:07:16 +00:00
AVR
BPF	[BPF] fix a bug in BPFMISimplifyPatchable pass with -O0	2020-01-30 08:28:39 -08:00
Generic
Hexagon
Inputs
Lanai
Mips
MIR
MSP430
NVPTX
PowerPC	[XCOFF][AIX] Support basic relocation type on AIX	2020-01-30 15:59:09 +00:00
RISCV
SPARC
SystemZ
Thumb
Thumb2	[ARM][LowOverheadLoops] Skip debug values	2020-01-30 11:51:58 +00:00
VE	[VE] (conditional) branch modification & isel patterns	2020-01-29 17:40:57 +01:00
WebAssembly	[WebAssembly] Preserve debug frame base information through register coloring	2020-01-28 16:58:15 -08:00
WinCFGuard
WinEH
X86	[DAG] SimplifyMultipleUseDemandedBits - peek through unused ISD::INSERT_SUBVECTOR subvectors	2020-01-31 18:57:22 +00:00
XCore