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399 lines
15 KiB
C++
399 lines
15 KiB
C++
//===--------------- PPCVSXFMAMutate.cpp - VSX FMA Mutation ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass mutates the form of VSX FMA instructions to avoid unnecessary
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// copies.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/PPCPredicates.h"
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#include "PPC.h"
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#include "PPCInstrBuilder.h"
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#include "PPCInstrInfo.h"
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#include "PPCMachineFunctionInfo.h"
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#include "PPCTargetMachine.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/LiveIntervals.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/CodeGen/ScheduleDAG.h"
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#include "llvm/CodeGen/SlotIndexes.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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// Temporarily disable FMA mutation by default, since it doesn't handle
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// cross-basic-block intervals well.
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// See: http://lists.llvm.org/pipermail/llvm-dev/2016-February/095669.html
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// http://reviews.llvm.org/D17087
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static cl::opt<bool> DisableVSXFMAMutate(
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"disable-ppc-vsx-fma-mutation",
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cl::desc("Disable VSX FMA instruction mutation"), cl::init(true),
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cl::Hidden);
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#define DEBUG_TYPE "ppc-vsx-fma-mutate"
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namespace llvm { namespace PPC {
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int getAltVSXFMAOpcode(uint16_t Opcode);
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} }
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namespace {
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// PPCVSXFMAMutate pass - For copies between VSX registers and non-VSX registers
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// (Altivec and scalar floating-point registers), we need to transform the
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// copies into subregister copies with other restrictions.
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struct PPCVSXFMAMutate : public MachineFunctionPass {
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static char ID;
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PPCVSXFMAMutate() : MachineFunctionPass(ID) {
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initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
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}
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LiveIntervals *LIS;
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const PPCInstrInfo *TII;
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protected:
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bool processBlock(MachineBasicBlock &MBB) {
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bool Changed = false;
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MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
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const TargetRegisterInfo *TRI = &TII->getRegisterInfo();
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for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
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I != IE; ++I) {
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MachineInstr &MI = *I;
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// The default (A-type) VSX FMA form kills the addend (it is taken from
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// the target register, which is then updated to reflect the result of
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// the FMA). If the instruction, however, kills one of the registers
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// used for the product, then we can use the M-form instruction (which
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// will take that value from the to-be-defined register).
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int AltOpc = PPC::getAltVSXFMAOpcode(MI.getOpcode());
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if (AltOpc == -1)
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continue;
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// This pass is run after register coalescing, and so we're looking for
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// a situation like this:
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// ...
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// %5 = COPY %9; VSLRC:%5,%9
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// %5<def,tied1> = XSMADDADP %5<tied0>, %17, %16,
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// implicit %rm; VSLRC:%5,%17,%16
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// ...
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// %9<def,tied1> = XSMADDADP %9<tied0>, %17, %19,
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// implicit %rm; VSLRC:%9,%17,%19
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// ...
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// Where we can eliminate the copy by changing from the A-type to the
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// M-type instruction. Specifically, for this example, this means:
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// %5<def,tied1> = XSMADDADP %5<tied0>, %17, %16,
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// implicit %rm; VSLRC:%5,%17,%16
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// is replaced by:
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// %16<def,tied1> = XSMADDMDP %16<tied0>, %18, %9,
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// implicit %rm; VSLRC:%16,%18,%9
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// and we remove: %5 = COPY %9; VSLRC:%5,%9
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SlotIndex FMAIdx = LIS->getInstructionIndex(MI);
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VNInfo *AddendValNo =
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LIS->getInterval(MI.getOperand(1).getReg()).Query(FMAIdx).valueIn();
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// This can be null if the register is undef.
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if (!AddendValNo)
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continue;
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MachineInstr *AddendMI = LIS->getInstructionFromIndex(AddendValNo->def);
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// The addend and this instruction must be in the same block.
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if (!AddendMI || AddendMI->getParent() != MI.getParent())
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continue;
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// The addend must be a full copy within the same register class.
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if (!AddendMI->isFullCopy())
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continue;
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unsigned AddendSrcReg = AddendMI->getOperand(1).getReg();
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if (TargetRegisterInfo::isVirtualRegister(AddendSrcReg)) {
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if (MRI.getRegClass(AddendMI->getOperand(0).getReg()) !=
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MRI.getRegClass(AddendSrcReg))
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continue;
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} else {
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// If AddendSrcReg is a physical register, make sure the destination
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// register class contains it.
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if (!MRI.getRegClass(AddendMI->getOperand(0).getReg())
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->contains(AddendSrcReg))
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continue;
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}
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// In theory, there could be other uses of the addend copy before this
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// fma. We could deal with this, but that would require additional
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// logic below and I suspect it will not occur in any relevant
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// situations. Additionally, check whether the copy source is killed
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// prior to the fma. In order to replace the addend here with the
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// source of the copy, it must still be live here. We can't use
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// interval testing for a physical register, so as long as we're
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// walking the MIs we may as well test liveness here.
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//
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// FIXME: There is a case that occurs in practice, like this:
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// %9 = COPY %f1; VSSRC:%9
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// ...
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// %6 = COPY %9; VSSRC:%6,%9
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// %7 = COPY %9; VSSRC:%7,%9
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// %9<def,tied1> = XSMADDASP %9<tied0>, %1, %4; VSSRC:
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// %6<def,tied1> = XSMADDASP %6<tied0>, %1, %2; VSSRC:
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// %7<def,tied1> = XSMADDASP %7<tied0>, %1, %3; VSSRC:
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// which prevents an otherwise-profitable transformation.
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bool OtherUsers = false, KillsAddendSrc = false;
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for (auto J = std::prev(I), JE = MachineBasicBlock::iterator(AddendMI);
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J != JE; --J) {
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if (J->readsVirtualRegister(AddendMI->getOperand(0).getReg())) {
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OtherUsers = true;
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break;
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}
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if (J->modifiesRegister(AddendSrcReg, TRI) ||
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J->killsRegister(AddendSrcReg, TRI)) {
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KillsAddendSrc = true;
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break;
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}
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}
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if (OtherUsers || KillsAddendSrc)
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continue;
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// The transformation doesn't work well with things like:
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// %5 = A-form-op %5, %11, %5;
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// unless %11 is also a kill, so skip when it is not,
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// and check operand 3 to see it is also a kill to handle the case:
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// %5 = A-form-op %5, %5, %11;
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// where %5 and %11 are both kills. This case would be skipped
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// otherwise.
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unsigned OldFMAReg = MI.getOperand(0).getReg();
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// Find one of the product operands that is killed by this instruction.
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unsigned KilledProdOp = 0, OtherProdOp = 0;
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unsigned Reg2 = MI.getOperand(2).getReg();
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unsigned Reg3 = MI.getOperand(3).getReg();
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if (LIS->getInterval(Reg2).Query(FMAIdx).isKill()
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&& Reg2 != OldFMAReg) {
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KilledProdOp = 2;
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OtherProdOp = 3;
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} else if (LIS->getInterval(Reg3).Query(FMAIdx).isKill()
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&& Reg3 != OldFMAReg) {
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KilledProdOp = 3;
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OtherProdOp = 2;
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}
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// If there are no usable killed product operands, then this
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// transformation is likely not profitable.
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if (!KilledProdOp)
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continue;
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// If the addend copy is used only by this MI, then the addend source
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// register is likely not live here. This could be fixed (based on the
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// legality checks above, the live range for the addend source register
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// could be extended), but it seems likely that such a trivial copy can
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// be coalesced away later, and thus is not worth the effort.
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if (TargetRegisterInfo::isVirtualRegister(AddendSrcReg) &&
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!LIS->getInterval(AddendSrcReg).liveAt(FMAIdx))
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continue;
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// Transform: (O2 * O3) + O1 -> (O2 * O1) + O3.
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unsigned KilledProdReg = MI.getOperand(KilledProdOp).getReg();
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unsigned OtherProdReg = MI.getOperand(OtherProdOp).getReg();
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unsigned AddSubReg = AddendMI->getOperand(1).getSubReg();
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unsigned KilledProdSubReg = MI.getOperand(KilledProdOp).getSubReg();
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unsigned OtherProdSubReg = MI.getOperand(OtherProdOp).getSubReg();
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bool AddRegKill = AddendMI->getOperand(1).isKill();
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bool KilledProdRegKill = MI.getOperand(KilledProdOp).isKill();
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bool OtherProdRegKill = MI.getOperand(OtherProdOp).isKill();
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bool AddRegUndef = AddendMI->getOperand(1).isUndef();
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bool KilledProdRegUndef = MI.getOperand(KilledProdOp).isUndef();
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bool OtherProdRegUndef = MI.getOperand(OtherProdOp).isUndef();
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// If there isn't a class that fits, we can't perform the transform.
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// This is needed for correctness with a mixture of VSX and Altivec
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// instructions to make sure that a low VSX register is not assigned to
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// the Altivec instruction.
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if (!MRI.constrainRegClass(KilledProdReg,
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MRI.getRegClass(OldFMAReg)))
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continue;
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assert(OldFMAReg == AddendMI->getOperand(0).getReg() &&
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"Addend copy not tied to old FMA output!");
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DEBUG(dbgs() << "VSX FMA Mutation:\n " << MI);
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MI.getOperand(0).setReg(KilledProdReg);
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MI.getOperand(1).setReg(KilledProdReg);
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MI.getOperand(3).setReg(AddendSrcReg);
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MI.getOperand(0).setSubReg(KilledProdSubReg);
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MI.getOperand(1).setSubReg(KilledProdSubReg);
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MI.getOperand(3).setSubReg(AddSubReg);
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MI.getOperand(1).setIsKill(KilledProdRegKill);
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MI.getOperand(3).setIsKill(AddRegKill);
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MI.getOperand(1).setIsUndef(KilledProdRegUndef);
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MI.getOperand(3).setIsUndef(AddRegUndef);
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MI.setDesc(TII->get(AltOpc));
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// If the addend is also a multiplicand, replace it with the addend
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// source in both places.
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if (OtherProdReg == AddendMI->getOperand(0).getReg()) {
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MI.getOperand(2).setReg(AddendSrcReg);
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MI.getOperand(2).setSubReg(AddSubReg);
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MI.getOperand(2).setIsKill(AddRegKill);
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MI.getOperand(2).setIsUndef(AddRegUndef);
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} else {
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MI.getOperand(2).setReg(OtherProdReg);
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MI.getOperand(2).setSubReg(OtherProdSubReg);
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MI.getOperand(2).setIsKill(OtherProdRegKill);
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MI.getOperand(2).setIsUndef(OtherProdRegUndef);
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}
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DEBUG(dbgs() << " -> " << MI);
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// The killed product operand was killed here, so we can reuse it now
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// for the result of the fma.
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LiveInterval &FMAInt = LIS->getInterval(OldFMAReg);
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VNInfo *FMAValNo = FMAInt.getVNInfoAt(FMAIdx.getRegSlot());
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for (auto UI = MRI.reg_nodbg_begin(OldFMAReg), UE = MRI.reg_nodbg_end();
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UI != UE;) {
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MachineOperand &UseMO = *UI;
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MachineInstr *UseMI = UseMO.getParent();
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++UI;
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// Don't replace the result register of the copy we're about to erase.
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if (UseMI == AddendMI)
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continue;
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UseMO.substVirtReg(KilledProdReg, KilledProdSubReg, *TRI);
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}
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// Extend the live intervals of the killed product operand to hold the
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// fma result.
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LiveInterval &NewFMAInt = LIS->getInterval(KilledProdReg);
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for (LiveInterval::iterator AI = FMAInt.begin(), AE = FMAInt.end();
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AI != AE; ++AI) {
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// Don't add the segment that corresponds to the original copy.
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if (AI->valno == AddendValNo)
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continue;
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VNInfo *NewFMAValNo =
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NewFMAInt.getNextValue(AI->start,
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LIS->getVNInfoAllocator());
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NewFMAInt.addSegment(LiveInterval::Segment(AI->start, AI->end,
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NewFMAValNo));
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}
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DEBUG(dbgs() << " extended: " << NewFMAInt << '\n');
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// Extend the live interval of the addend source (it might end at the
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// copy to be removed, or somewhere in between there and here). This
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// is necessary only if it is a physical register.
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if (!TargetRegisterInfo::isVirtualRegister(AddendSrcReg))
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for (MCRegUnitIterator Units(AddendSrcReg, TRI); Units.isValid();
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++Units) {
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unsigned Unit = *Units;
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LiveRange &AddendSrcRange = LIS->getRegUnit(Unit);
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AddendSrcRange.extendInBlock(LIS->getMBBStartIdx(&MBB),
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FMAIdx.getRegSlot());
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DEBUG(dbgs() << " extended: " << AddendSrcRange << '\n');
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}
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FMAInt.removeValNo(FMAValNo);
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DEBUG(dbgs() << " trimmed: " << FMAInt << '\n');
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// Remove the (now unused) copy.
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DEBUG(dbgs() << " removing: " << *AddendMI << '\n');
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LIS->RemoveMachineInstrFromMaps(*AddendMI);
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AddendMI->eraseFromParent();
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Changed = true;
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}
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return Changed;
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}
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public:
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bool runOnMachineFunction(MachineFunction &MF) override {
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if (skipFunction(MF.getFunction()))
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return false;
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// If we don't have VSX then go ahead and return without doing
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// anything.
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const PPCSubtarget &STI = MF.getSubtarget<PPCSubtarget>();
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if (!STI.hasVSX())
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return false;
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LIS = &getAnalysis<LiveIntervals>();
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TII = STI.getInstrInfo();
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bool Changed = false;
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if (DisableVSXFMAMutate)
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return Changed;
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for (MachineFunction::iterator I = MF.begin(); I != MF.end();) {
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MachineBasicBlock &B = *I++;
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if (processBlock(B))
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Changed = true;
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}
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return Changed;
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.addRequired<LiveIntervals>();
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AU.addPreserved<LiveIntervals>();
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AU.addRequired<SlotIndexes>();
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AU.addPreserved<SlotIndexes>();
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AU.addRequired<MachineDominatorTree>();
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AU.addPreserved<MachineDominatorTree>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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};
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}
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INITIALIZE_PASS_BEGIN(PPCVSXFMAMutate, DEBUG_TYPE,
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"PowerPC VSX FMA Mutation", false, false)
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INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
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INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
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INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
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INITIALIZE_PASS_END(PPCVSXFMAMutate, DEBUG_TYPE,
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"PowerPC VSX FMA Mutation", false, false)
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char &llvm::PPCVSXFMAMutateID = PPCVSXFMAMutate::ID;
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char PPCVSXFMAMutate::ID = 0;
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FunctionPass *llvm::createPPCVSXFMAMutatePass() {
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return new PPCVSXFMAMutate();
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}
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