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816 lines
32 KiB
TableGen
816 lines
32 KiB
TableGen
//===- X86ScheduleAtom.td - X86 Atom Scheduling Definitions -*- tablegen -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the schedule class data for the Intel Atom
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// in order (Saltwell-32nm/Bonnell-45nm) processors.
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//
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//===----------------------------------------------------------------------===//
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//
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// Scheduling information derived from the "Intel 64 and IA32 Architectures
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// Optimization Reference Manual", Chapter 13, Section 4.
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// Atom machine model.
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def AtomModel : SchedMachineModel {
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let IssueWidth = 2; // Allows 2 instructions per scheduling group.
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let MicroOpBufferSize = 0; // In-order execution, always hide latency.
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let LoadLatency = 3; // Expected cycles, may be overriden.
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let HighLatency = 30;// Expected, may be overriden.
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// On the Atom, the throughput for taken branches is 2 cycles. For small
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// simple loops, expand by a small factor to hide the backedge cost.
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let LoopMicroOpBufferSize = 10;
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let PostRAScheduler = 1;
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let CompleteModel = 0;
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}
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let SchedModel = AtomModel in {
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// Functional Units
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def AtomPort0 : ProcResource<1>; // ALU: ALU0, shift/rotate, load/store
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// SIMD/FP: SIMD ALU, Shuffle,SIMD/FP multiply, divide
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def AtomPort1 : ProcResource<1>; // ALU: ALU1, bit processing, jump, and LEA
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// SIMD/FP: SIMD ALU, FP Adder
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def AtomPort01 : ProcResGroup<[AtomPort0, AtomPort1]>;
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// Loads are 3 cycles, so ReadAfterLd registers needn't be available until 3
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// cycles after the memory operand.
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def : ReadAdvance<ReadAfterLd, 3>;
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// Many SchedWrites are defined in pairs with and without a folded load.
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// Instructions with folded loads are usually micro-fused, so they only appear
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// as two micro-ops when dispatched by the schedulers.
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// This multiclass defines the resource usage for variants with and without
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// folded loads.
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multiclass AtomWriteResPair<X86FoldableSchedWrite SchedRW,
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list<ProcResourceKind> RRPorts,
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list<ProcResourceKind> RMPorts,
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int RRLat = 1, int RMLat = 1,
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list<int> RRRes = [1],
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list<int> RMRes = [1]> {
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// Register variant is using a single cycle on ExePort.
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def : WriteRes<SchedRW, RRPorts> {
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let Latency = RRLat;
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let ResourceCycles = RRRes;
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}
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// Memory variant also uses a cycle on JLAGU and adds 3 cycles to the
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// latency.
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def : WriteRes<SchedRW.Folded, RMPorts> {
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let Latency = RMLat;
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let ResourceCycles = RMRes;
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}
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}
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// A folded store needs a cycle on Port0 for the store data.
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def : WriteRes<WriteRMW, [AtomPort0]>;
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////////////////////////////////////////////////////////////////////////////////
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// Arithmetic.
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////////////////////////////////////////////////////////////////////////////////
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defm : AtomWriteResPair<WriteALU, [AtomPort01], [AtomPort0]>;
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defm : AtomWriteResPair<WriteIMul, [AtomPort01], [AtomPort01], 7, 7, [7], [7]>;
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defm : AtomWriteResPair<WriteIDiv, [AtomPort01], [AtomPort01], 62, 62, [62], [62]>;
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defm : AtomWriteResPair<WriteCRC32, [AtomPort01], [AtomPort01]>; // NOTE: Doesn't exist on Atom.
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defm : AtomWriteResPair<WriteCMOV, [AtomPort01], [AtomPort0]>;
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def : WriteRes<WriteSETCC, [AtomPort01]>;
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def : WriteRes<WriteSETCCStore, [AtomPort01]> {
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let Latency = 2;
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let ResourceCycles = [2];
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}
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def : WriteRes<WriteIMulH, [AtomPort01]>; // NOTE: Doesn't exist on Atom.
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// This is for simple LEAs with one or two input operands.
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def : WriteRes<WriteLEA, [AtomPort1]>;
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def AtomWriteIMul16Ld : SchedWriteRes<[AtomPort01]> {
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let Latency = 8;
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let ResourceCycles = [8];
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}
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def : InstRW<[AtomWriteIMul16Ld], (instrs MUL16m, IMUL16m)>;
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def AtomWriteIMul32 : SchedWriteRes<[AtomPort01]> {
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let Latency = 6;
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let ResourceCycles = [6];
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}
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def : InstRW<[AtomWriteIMul32], (instrs MUL32r, IMUL32r)>;
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def AtomWriteIMul64 : SchedWriteRes<[AtomPort01]> {
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let Latency = 12;
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let ResourceCycles = [12];
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}
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def : InstRW<[AtomWriteIMul64], (instrs MUL64r, IMUL64r, IMUL64rr, IMUL64rm,
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MUL64m, IMUL64m)>;
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def AtomWriteIMul64I : SchedWriteRes<[AtomPort01]> {
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let Latency = 14;
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let ResourceCycles = [14];
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}
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def : InstRW<[AtomWriteIMul64I], (instrs IMUL64rri8, IMUL64rri32,
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IMUL64rmi8, IMUL64rmi32)>;
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def AtomWriteDiv : SchedWriteRes<[AtomPort01]> {
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let Latency = 50;
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let ResourceCycles = [50];
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}
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def : InstRW<[AtomWriteDiv], (instrs DIV8r,
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DIV16r, DIV16m,
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DIV32r, DIV32m)>;
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def AtomWriteDiv8Ld : SchedWriteRes<[AtomPort01]> {
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let Latency = 68;
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let ResourceCycles = [68];
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}
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def : InstRW<[AtomWriteDiv8Ld], (instrs DIV8m)>;
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def AtomWriteIDiv64 : SchedWriteRes<[AtomPort01]> {
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let Latency = 130;
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let ResourceCycles = [130];
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}
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def : InstRW<[AtomWriteIDiv64], (instrs DIV64r, IDIV64r,
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DIV64m, IDIV64m)>;
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// Bit counts.
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defm : AtomWriteResPair<WriteBitScan, [AtomPort01], [AtomPort01], 16, 16, [16], [16]>;
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defm : AtomWriteResPair<WritePOPCNT, [AtomPort01], [AtomPort01]>; // NOTE: Doesn't exist on Atom.
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defm : AtomWriteResPair<WriteLZCNT, [AtomPort01], [AtomPort01]>; // NOTE: Doesn't exist on Atom.
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defm : AtomWriteResPair<WriteTZCNT, [AtomPort01], [AtomPort01]>; // NOTE: Doesn't exist on Atom.
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// BMI1 BEXTR, BMI2 BZHI
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defm : AtomWriteResPair<WriteBEXTR, [AtomPort01], [AtomPort01]>; // NOTE: Doesn't exist on Atom.
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defm : AtomWriteResPair<WriteBZHI, [AtomPort01], [AtomPort01]>; // NOTE: Doesn't exist on Atom.
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////////////////////////////////////////////////////////////////////////////////
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// Integer shifts and rotates.
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////////////////////////////////////////////////////////////////////////////////
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defm : AtomWriteResPair<WriteShift, [AtomPort0], [AtomPort0]>;
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////////////////////////////////////////////////////////////////////////////////
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// Loads, stores, and moves, not folded with other operations.
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////////////////////////////////////////////////////////////////////////////////
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def : WriteRes<WriteLoad, [AtomPort0]>;
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def : WriteRes<WriteStore, [AtomPort0]>;
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def : WriteRes<WriteMove, [AtomPort01]>;
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// Treat misc copies as a move.
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def : InstRW<[WriteMove], (instrs COPY)>;
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////////////////////////////////////////////////////////////////////////////////
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// Idioms that clear a register, like xorps %xmm0, %xmm0.
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// These can often bypass execution ports completely.
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////////////////////////////////////////////////////////////////////////////////
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def : WriteRes<WriteZero, []>;
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////////////////////////////////////////////////////////////////////////////////
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// Branches don't produce values, so they have no latency, but they still
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// consume resources. Indirect branches can fold loads.
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////////////////////////////////////////////////////////////////////////////////
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defm : AtomWriteResPair<WriteJump, [AtomPort1], [AtomPort1]>;
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////////////////////////////////////////////////////////////////////////////////
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// Special case scheduling classes.
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////////////////////////////////////////////////////////////////////////////////
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def : WriteRes<WriteSystem, [AtomPort01]> { let Latency = 100; }
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def : WriteRes<WriteMicrocoded, [AtomPort01]> { let Latency = 100; }
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def : WriteRes<WriteFence, [AtomPort0]>;
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// Nops don't have dependencies, so there's no actual latency, but we set this
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// to '1' to tell the scheduler that the nop uses an ALU slot for a cycle.
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def : WriteRes<WriteNop, [AtomPort01]>;
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////////////////////////////////////////////////////////////////////////////////
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// Floating point. This covers both scalar and vector operations.
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////////////////////////////////////////////////////////////////////////////////
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def : WriteRes<WriteFLoad, [AtomPort0]>;
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def : WriteRes<WriteFStore, [AtomPort0]>;
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def : WriteRes<WriteFMove, [AtomPort01]>;
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defm : AtomWriteResPair<WriteFAdd, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
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defm : AtomWriteResPair<WriteFCmp, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
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defm : AtomWriteResPair<WriteFCom, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
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defm : AtomWriteResPair<WriteFMul, [AtomPort0], [AtomPort0], 4, 4, [4], [4]>;
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defm : AtomWriteResPair<WriteFRcp, [AtomPort0], [AtomPort0], 4, 4, [4], [4]>;
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defm : AtomWriteResPair<WriteFRsqrt, [AtomPort0], [AtomPort0], 4, 4, [4], [4]>;
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defm : AtomWriteResPair<WriteFDiv, [AtomPort01], [AtomPort01], 34, 34, [34], [34]>;
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defm : AtomWriteResPair<WriteFSqrt, [AtomPort01], [AtomPort01], 34, 34, [34], [34]>;
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defm : AtomWriteResPair<WriteFSign, [AtomPort1], [AtomPort1]>;
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defm : AtomWriteResPair<WriteFLogic, [AtomPort01], [AtomPort0]>;
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defm : AtomWriteResPair<WriteFShuffle, [AtomPort0], [AtomPort0]>;
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defm : AtomWriteResPair<WriteFVarShuffle, [AtomPort0], [AtomPort0]>; // NOTE: Doesn't exist on Atom.
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defm : AtomWriteResPair<WriteFMA, [AtomPort0], [AtomPort0]>; // NOTE: Doesn't exist on Atom.
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defm : AtomWriteResPair<WriteFBlend, [AtomPort0], [AtomPort0]>; // NOTE: Doesn't exist on Atom.
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defm : AtomWriteResPair<WriteFVarBlend, [AtomPort0], [AtomPort0]>; // NOTE: Doesn't exist on Atom.
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defm : AtomWriteResPair<WriteFShuffle256, [AtomPort0], [AtomPort0]>; // NOTE: Doesn't exist on Atom.
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defm : AtomWriteResPair<WriteFVarShuffle256, [AtomPort0], [AtomPort0]>; // NOTE: Doesn't exist on Atom.
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////////////////////////////////////////////////////////////////////////////////
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// Conversions.
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////////////////////////////////////////////////////////////////////////////////
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defm : AtomWriteResPair<WriteCvtF2I, [AtomPort01], [AtomPort01], 8, 9, [8], [9]>; // Float -> Integer.
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defm : AtomWriteResPair<WriteCvtI2F, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>; // Integer -> Float.
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defm : AtomWriteResPair<WriteCvtF2F, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>; // Float -> Float size conversion.
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////////////////////////////////////////////////////////////////////////////////
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// Vector integer operations.
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////////////////////////////////////////////////////////////////////////////////
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def : WriteRes<WriteVecLoad, [AtomPort0]>;
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def : WriteRes<WriteVecStore, [AtomPort0]>;
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def : WriteRes<WriteVecMove, [AtomPort01]>;
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defm : AtomWriteResPair<WriteVecALU, [AtomPort01], [AtomPort0], 1, 1>;
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defm : AtomWriteResPair<WriteVecLogic, [AtomPort01], [AtomPort0], 1, 1>;
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defm : AtomWriteResPair<WriteVecShift, [AtomPort01], [AtomPort01], 2, 3, [2], [3]>;
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defm : AtomWriteResPair<WriteVecIMul, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
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defm : AtomWriteResPair<WritePMULLD, [AtomPort01], [AtomPort0], 1, 1>;
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defm : AtomWriteResPair<WriteMPSAD, [AtomPort01], [AtomPort0], 1, 1>;
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defm : AtomWriteResPair<WritePSADBW, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
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defm : AtomWriteResPair<WriteShuffle, [AtomPort0], [AtomPort0], 1, 1>;
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defm : AtomWriteResPair<WriteVarShuffle, [AtomPort01], [AtomPort01], 4, 5, [4], [5]>;
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defm : AtomWriteResPair<WriteBlend, [AtomPort0], [AtomPort0]>; // NOTE: Doesn't exist on Atom.
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defm : AtomWriteResPair<WriteVarBlend, [AtomPort0], [AtomPort0]>; // NOTE: Doesn't exist on Atom.
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defm : AtomWriteResPair<WriteShuffle256, [AtomPort0], [AtomPort0]>; // NOTE: Doesn't exist on Atom.
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defm : AtomWriteResPair<WriteVarShuffle256, [AtomPort0], [AtomPort0]>; // NOTE: Doesn't exist on Atom.
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defm : AtomWriteResPair<WriteVarVecShift, [AtomPort0], [AtomPort0]>; // NOTE: Doesn't exist on Atom.
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////////////////////////////////////////////////////////////////////////////////
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// SSE42 String instructions.
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////////////////////////////////////////////////////////////////////////////////
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defm : AtomWriteResPair<WritePCmpIStrI, [AtomPort01], [AtomPort01]>; // NOTE: Doesn't exist on Atom.
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defm : AtomWriteResPair<WritePCmpIStrM, [AtomPort01], [AtomPort01]>; // NOTE: Doesn't exist on Atom.
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defm : AtomWriteResPair<WritePCmpEStrI, [AtomPort01], [AtomPort01]>; // NOTE: Doesn't exist on Atom.
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defm : AtomWriteResPair<WritePCmpEStrM, [AtomPort01], [AtomPort01]>; // NOTE: Doesn't exist on Atom.
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////////////////////////////////////////////////////////////////////////////////
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// MOVMSK Instructions.
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////////////////////////////////////////////////////////////////////////////////
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def : WriteRes<WriteFMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; }
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def : WriteRes<WriteVecMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; }
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def : WriteRes<WriteMMXMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; }
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////////////////////////////////////////////////////////////////////////////////
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// AES Instructions.
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////////////////////////////////////////////////////////////////////////////////
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defm : AtomWriteResPair<WriteAESIMC, [AtomPort01], [AtomPort01]>; // NOTE: Doesn't exist on Atom.
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defm : AtomWriteResPair<WriteAESKeyGen, [AtomPort01], [AtomPort01]>; // NOTE: Doesn't exist on Atom.
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defm : AtomWriteResPair<WriteAESDecEnc, [AtomPort01], [AtomPort01]>; // NOTE: Doesn't exist on Atom.
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////////////////////////////////////////////////////////////////////////////////
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// Horizontal add/sub instructions.
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////////////////////////////////////////////////////////////////////////////////
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defm : AtomWriteResPair<WriteFHAdd, [AtomPort01], [AtomPort01], 8, 9, [8], [9]>;
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defm : AtomWriteResPair<WritePHAdd, [AtomPort01], [AtomPort01], 7, 8, [7], [8]>;
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////////////////////////////////////////////////////////////////////////////////
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// Carry-less multiplication instructions.
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////////////////////////////////////////////////////////////////////////////////
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defm : AtomWriteResPair<WriteCLMul, [AtomPort01], [AtomPort01]>; // NOTE: Doesn't exist on Atom.
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////////////////////////////////////////////////////////////////////////////////
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// Special Cases.
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////////////////////////////////////////////////////////////////////////////////
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// Port0
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def AtomWrite0_1 : SchedWriteRes<[AtomPort0]> {
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let Latency = 1;
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let ResourceCycles = [1];
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}
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def : InstRW<[AtomWrite0_1], (instrs FXAM,
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BSWAP32r, BSWAP64r,
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DEC8m, DEC16m, DEC32m, DEC64m,
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INC8m, INC16m, INC32m, INC64m,
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MOVSX64rr32,
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MMX_MOVD64rr,
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MMX_MOVD64to64rr,
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MMX_PSHUFBrr, MMX_PSHUFBrm,
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MOVDI2PDIrr, MOVDI2PDIrm,
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MOV64toPQIrr, MOV64toPQIrm,
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MOV64toSDrr, MOV64toSDrm, MOVSDto64mr,
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MOVDI2SSrr, MOVDI2SSrm,
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MOVPDI2DImr, MOVPQIto64mr, MOVSS2DImr, MOVQI2PQIrm, MOVPQI2QImr)>;
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def : InstRW<[AtomWrite0_1], (instregex "(ADC|ADD|AND|NEG|NOT|OR|SBB|SUB|XOR)(8|16|32|64)m",
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"(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m",
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"MOV(S|Z)X(32|64)(rr|rm)(8|8_NOREX|16)",
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"LD_F(P)?(16|32|64)?(m|rr)",
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"MMX_PAVG(B|W)irm",
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"MMX_P(MAX|MIN)(UB|SW)irm",
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"MMX_PSIGN(B|D|W)rm")>;
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def AtomWrite0_3 : SchedWriteRes<[AtomPort0]> {
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let Latency = 3;
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let ResourceCycles = [3];
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}
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def : InstRW<[AtomWrite0_3], (instrs MMX_MOVD64from64rr, MMX_MOVD64grr,
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MOVPDI2DIrr, MOVPQIto64rr,
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MOVSDto64rr, MOVSS2DIrr)>;
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def AtomWrite0_4 : SchedWriteRes<[AtomPort0]> {
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let Latency = 4;
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let ResourceCycles = [4];
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}
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def : InstRW<[AtomWrite0_4], (instrs MMX_PMADDUBSWrr, MMX_PMADDUBSWrm,
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MMX_PMADDWDirr, MMX_PMADDWDirm,
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MMX_PMULHRSWrr, MMX_PMULHRSWrm,
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MMX_PMULHUWirr, MMX_PMULHUWirm,
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MMX_PMULHWirr, MMX_PMULHWirm,
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MMX_PMULLWirr, MMX_PMULLWirm,
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MMX_PMULUDQirr, MMX_PMULUDQirm)>;
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def AtomWrite0_5 : SchedWriteRes<[AtomPort0]> {
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let Latency = 5;
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let ResourceCycles = [5];
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}
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def : InstRW<[AtomWrite0_5], (instregex "IMUL32(rm|rr)",
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"MUL(PS|SD)(rr|rm)(_Int)?")>;
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// Port1
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def AtomWrite1_1 : SchedWriteRes<[AtomPort1]> {
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let Latency = 1;
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let ResourceCycles = [1];
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}
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def : InstRW<[AtomWrite1_1], (instrs FCOMPP)>;
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def : InstRW<[AtomWrite1_1], (instregex "UCOM_F(P|PP)?r",
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"BT(C|R|S)?(16|32|64)(rr|ri8)")>;
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def AtomWrite1_5 : SchedWriteRes<[AtomPort1]> {
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let Latency = 5;
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let ResourceCycles = [5];
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}
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def : InstRW<[AtomWrite1_5], (instrs MMX_CVTPI2PSirr, MMX_CVTPI2PSirm,
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MMX_CVTPS2PIirr, MMX_CVTTPS2PIirr)>;
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// Port0 and Port1
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def AtomWrite0_1_1 : SchedWriteRes<[AtomPort0, AtomPort1]> {
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let Latency = 1;
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let ResourceCycles = [1, 1];
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}
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def : InstRW<[AtomWrite0_1_1], (instrs POP32r, POP64r,
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POP16rmr, POP32rmr, POP64rmr,
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PUSH16r, PUSH32r, PUSH64r,
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PUSHi16, PUSHi32,
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PUSH16rmr, PUSH32rmr, PUSH64rmr,
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PUSH16i8, PUSH32i8, PUSH64i8, PUSH64i32,
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XCH_F)>;
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def : InstRW<[AtomWrite0_1_1], (instregex "RETI(L|Q|W)$",
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"IRET(16|32|64)?")>;
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def AtomWrite0_1_5 : SchedWriteRes<[AtomPort0, AtomPort1]> {
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let Latency = 5;
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let ResourceCycles = [5, 5];
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}
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def : InstRW<[AtomWrite0_1_5], (instrs MMX_CVTPS2PIirm, MMX_CVTTPS2PIirm)>;
|
|
def : InstRW<[AtomWrite0_1_5], (instregex "ILD_F(16|32|64)")>;
|
|
|
|
// Port0 or Port1
|
|
def AtomWrite01_1 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 1;
|
|
let ResourceCycles = [1];
|
|
}
|
|
def : InstRW<[AtomWrite01_1], (instrs FDECSTP, FFREE, FFREEP, FINCSTP, LD_F0, WAIT,
|
|
LFENCE,
|
|
STOSB, STOSL, STOSQ, STOSW,
|
|
MOVSSrr, MOVSSrr_REV,
|
|
PSLLDQri, PSRLDQri)>;
|
|
def : InstRW<[AtomWrite01_1], (instregex "(MMX_)?PS(LL|RA|RL)(D|Q|W)ri",
|
|
"MMX_PACK(SSDW|SSWB|USWB)irr",
|
|
"MMX_PUNPCKH(BW|DQ|WD)irr")>;
|
|
|
|
def AtomWrite01_2 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 2;
|
|
let ResourceCycles = [2];
|
|
}
|
|
def : InstRW<[AtomWrite01_2], (instrs LEAVE, LEAVE64, POP16r,
|
|
PUSH16rmm, PUSH32rmm, PUSH64rmm,
|
|
LODSB, LODSL, LODSQ, LODSW,
|
|
SCASB, SCASL, SCASQ, SCASW,
|
|
SHLD32rrCL, SHRD32rrCL,
|
|
SHLD32rri8, SHRD32rri8)>;
|
|
def : InstRW<[AtomWrite01_2], (instregex "BT(C|R|S)(16|32|64)mi8",
|
|
"PUSH(CS|DS|ES|FS|GS|SS)(16|32|64)",
|
|
"XADD(8|16|32|64)rr",
|
|
"XCHG(8|16|32|64)(ar|rr)",
|
|
"(ST|ISTT)_F(P)?(16|32|64)?(m|rr)",
|
|
"MMX_P(ADD|SUB)Qirr",
|
|
"MOV(S|Z)X16rr8",
|
|
"MOV(UPS|UPD|DQU)mr",
|
|
"MASKMOVDQU(64)?",
|
|
"P(ADD|SUB)Qrr")>;
|
|
|
|
def AtomWrite01_3 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 3;
|
|
let ResourceCycles = [3];
|
|
}
|
|
def : InstRW<[AtomWrite01_3], (instrs CLD, LDDQUrm,
|
|
CMPSB, CMPSL, CMPSQ, CMPSW,
|
|
MOVSB, MOVSL, MOVSQ, MOVSW,
|
|
POP16rmm, POP32rmm, POP64rmm)>;
|
|
def : InstRW<[AtomWrite01_3], (instregex "XADD(8|16|32|64)rm",
|
|
"XCHG(8|16|32|64)rm",
|
|
"(MMX_)?PH(ADD|SUB)Drr",
|
|
"MOV(S|Z)X16rm8",
|
|
"MMX_P(ADD|SUB)Qirm",
|
|
"MOV(UPS|UPD|DQU)rm",
|
|
"P(ADD|SUB)Qrm")>;
|
|
|
|
def AtomWrite01_4 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 4;
|
|
let ResourceCycles = [4];
|
|
}
|
|
def : InstRW<[AtomWrite01_4], (instrs CBW, CWD, CWDE, CDQ, CDQE, CQO,
|
|
JCXZ, JECXZ, JRCXZ,
|
|
SHLD32mrCL, SHRD32mrCL,
|
|
SHLD32mri8, SHRD32mri8,
|
|
LD_F80m,
|
|
MMX_PSADBWirr, MMX_PSADBWirm)>;
|
|
def : InstRW<[AtomWrite01_4], (instregex "(MMX_)?PH(ADD|SUB)Drm",
|
|
"(MMX_)?PEXTRWrr(_REV)?")>;
|
|
|
|
def AtomWrite01_5 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 5;
|
|
let ResourceCycles = [5];
|
|
}
|
|
def : InstRW<[AtomWrite01_5], (instrs FLDCW16m, LDMXCSR,
|
|
MMX_EMMS)>;
|
|
def : InstRW<[AtomWrite01_5], (instregex "ST_FP80m",
|
|
"MMX_PH(ADD|SUB)S?Wrr")>;
|
|
|
|
def AtomWrite01_6 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 6;
|
|
let ResourceCycles = [6];
|
|
}
|
|
def : InstRW<[AtomWrite01_6], (instrs LD_F1, CMPXCHG8rm, INTO, XLAT,
|
|
SHLD16rrCL, SHRD16rrCL,
|
|
SHLD16rri8, SHRD16rri8,
|
|
SHLD16mrCL, SHRD16mrCL,
|
|
SHLD16mri8, SHRD16mri8,
|
|
ADDSUBPDrr, ADDSUBPDrm,
|
|
CVTPS2DQrr, CVTTPS2DQrr)>;
|
|
def : InstRW<[AtomWrite01_6], (instregex "IMUL16rr",
|
|
"IST_F(P)?(16|32|64)?m",
|
|
"MMX_PH(ADD|SUB)S?Wrm",
|
|
"(ADD|SUB|MAX|MIN)PDrr",
|
|
"CMPPDrri")>;
|
|
|
|
def AtomWrite01_7 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 7;
|
|
let ResourceCycles = [7];
|
|
}
|
|
def : InstRW<[AtomWrite01_7], (instrs AAD8i8,
|
|
CVTDQ2PDrr,
|
|
CVTPD2DQrr,
|
|
CVTPD2PSrr,
|
|
CVTPS2DQrm,
|
|
CVTPS2PDrr,
|
|
CVTTPD2DQrr,
|
|
CVTTPS2DQrm,
|
|
MMX_CVTPD2PIirr,
|
|
MMX_CVTPI2PDirr,
|
|
MMX_CVTTPD2PIirr)>;
|
|
def : InstRW<[AtomWrite01_7], (instregex "(ADD|SUB|MAX|MIN)PDrm",
|
|
"CMPPDrmi")>;
|
|
|
|
def AtomWrite01_8 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 8;
|
|
let ResourceCycles = [8];
|
|
}
|
|
def : InstRW<[AtomWrite01_8], (instrs LOOPE,
|
|
PUSHA16, PUSHA32,
|
|
SHLD64rrCL, SHRD64rrCL,
|
|
FNSTCW16m,
|
|
CVTDQ2PDrm,
|
|
CVTPD2DQrm,
|
|
CVTPD2PSrm,
|
|
CVTPS2PDrm,
|
|
CVTTPD2DQrm,
|
|
MMX_CVTPD2PIirm,
|
|
MMX_CVTPI2PDirm,
|
|
MMX_CVTTPD2PIirm)>;
|
|
|
|
def AtomWrite01_9 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 9;
|
|
let ResourceCycles = [9];
|
|
}
|
|
def : InstRW<[AtomWrite01_9], (instrs BT16mr, BT32mr, BT64mr,
|
|
POPA16, POPA32,
|
|
PUSHF16, PUSHF32, PUSHF64,
|
|
SHLD64mrCL, SHRD64mrCL,
|
|
SHLD64mri8, SHRD64mri8,
|
|
SHLD64rri8, SHRD64rri8,
|
|
CMPXCHG8rr,
|
|
MULPDrr, RCPPSr, RSQRTPSr)>;
|
|
def : InstRW<[AtomWrite01_9], (instregex "CMOV(B|BE|E|P|NB|NBE|NE|NP)_F",
|
|
"(U)?COM_FI", "TST_F",
|
|
"(U)?COMIS(D|S)rr",
|
|
"CVT(T)?SS2SI64rr(_Int)?")>;
|
|
|
|
def AtomWrite01_10 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 10;
|
|
let ResourceCycles = [10];
|
|
}
|
|
def : InstRW<[AtomWrite01_10], (instrs FLDL2E, FLDL2T, FLDLG2, FLDLN2, FLDPI,
|
|
MULPDrm, RCPPSm, RSQRTPSm)>;
|
|
def : InstRW<[AtomWrite01_10], (instregex "(U)?COMIS(D|S)rm",
|
|
"CVT(T)?SS2SI64rm(_Int)?")>;
|
|
|
|
def AtomWrite01_11 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 11;
|
|
let ResourceCycles = [11];
|
|
}
|
|
def : InstRW<[AtomWrite01_11], (instrs BOUNDS16rm, BOUNDS32rm)>;
|
|
def : InstRW<[AtomWrite01_11], (instregex "BT(C|R|S)(16|32|64)mr")>;
|
|
|
|
def AtomWrite01_13 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 13;
|
|
let ResourceCycles = [13];
|
|
}
|
|
def : InstRW<[AtomWrite01_13], (instrs AAA, AAS)>;
|
|
|
|
def AtomWrite01_14 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 14;
|
|
let ResourceCycles = [14];
|
|
}
|
|
def : InstRW<[AtomWrite01_14], (instrs CMPXCHG16rm, CMPXCHG32rm, CMPXCHG64rm)>;
|
|
|
|
def AtomWrite01_15 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 15;
|
|
let ResourceCycles = [15];
|
|
}
|
|
def : InstRW<[AtomWrite01_15], (instrs CMPXCHG16rr, CMPXCHG32rr, CMPXCHG64rr,
|
|
STMXCSR)>;
|
|
|
|
def AtomWrite01_17 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 17;
|
|
let ResourceCycles = [17];
|
|
}
|
|
def : InstRW<[AtomWrite01_17], (instrs LOOPNE, PAUSE)>;
|
|
|
|
def AtomWrite01_18 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 18;
|
|
let ResourceCycles = [18];
|
|
}
|
|
def : InstRW<[AtomWrite01_18], (instrs CMPXCHG8B, DAA, LOOP)>;
|
|
|
|
def AtomWrite01_20 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 20;
|
|
let ResourceCycles = [20];
|
|
}
|
|
def : InstRW<[AtomWrite01_20], (instrs DAS)>;
|
|
|
|
def AtomWrite01_21 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 21;
|
|
let ResourceCycles = [21];
|
|
}
|
|
def : InstRW<[AtomWrite01_21], (instrs AAM8i8, STD)>;
|
|
|
|
def AtomWrite01_22 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 22;
|
|
let ResourceCycles = [22];
|
|
}
|
|
def : InstRW<[AtomWrite01_22], (instrs CMPXCHG16B)>;
|
|
|
|
def AtomWrite01_23 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 23;
|
|
let ResourceCycles = [23];
|
|
}
|
|
def : InstRW<[AtomWrite01_23], (instrs ARPL16mr, ARPL16rr)>;
|
|
|
|
def AtomWrite01_25 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 25;
|
|
let ResourceCycles = [25];
|
|
}
|
|
def : InstRW<[AtomWrite01_25], (instrs FNCLEX, FXTRACT)>;
|
|
|
|
def AtomWrite01_26 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 26;
|
|
let ResourceCycles = [26];
|
|
}
|
|
def : InstRW<[AtomWrite01_26], (instrs POPF32, POPF64)>;
|
|
|
|
def AtomWrite01_29 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 29;
|
|
let ResourceCycles = [29];
|
|
}
|
|
def : InstRW<[AtomWrite01_29], (instregex "POP(DS|ES|FS|GS)(16|32|64)")>;
|
|
|
|
def AtomWrite01_30 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 30;
|
|
let ResourceCycles = [30];
|
|
}
|
|
def : InstRW<[AtomWrite01_30], (instrs RDTSC, RDTSCP)>;
|
|
|
|
def AtomWrite01_32 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 32;
|
|
let ResourceCycles = [32];
|
|
}
|
|
def : InstRW<[AtomWrite01_32], (instrs ENTER, POPF16)>;
|
|
|
|
def AtomWrite01_45 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 45;
|
|
let ResourceCycles = [45];
|
|
}
|
|
def : InstRW<[AtomWrite01_45], (instrs MONITORrrr)>;
|
|
|
|
def AtomWrite01_46 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 46;
|
|
let ResourceCycles = [46];
|
|
}
|
|
def : InstRW<[AtomWrite01_46], (instrs FRNDINT, MWAITrr, RDPMC)>;
|
|
|
|
def AtomWrite01_48 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 48;
|
|
let ResourceCycles = [48];
|
|
}
|
|
def : InstRW<[AtomWrite01_48], (instrs POPSS16, POPSS32)>;
|
|
|
|
def AtomWrite01_55 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 55;
|
|
let ResourceCycles = [55];
|
|
}
|
|
def : InstRW<[AtomWrite01_55], (instrs FPREM)>;
|
|
|
|
def AtomWrite01_59 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 59;
|
|
let ResourceCycles = [59];
|
|
}
|
|
def : InstRW<[AtomWrite01_59], (instrs INSB, INSL, INSW)>;
|
|
|
|
def AtomWrite01_62 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 62;
|
|
let ResourceCycles = [62];
|
|
}
|
|
def : InstRW<[AtomWrite01_62], (instregex "DIVSD(r|m)(_Int)?",
|
|
"SQRTSD(r|m)(_Int)?")>;
|
|
|
|
def AtomWrite01_63 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 63;
|
|
let ResourceCycles = [63];
|
|
}
|
|
def : InstRW<[AtomWrite01_63], (instrs FNINIT)>;
|
|
|
|
def AtomWrite01_68 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 68;
|
|
let ResourceCycles = [68];
|
|
}
|
|
def : InstRW<[AtomWrite01_68], (instrs OUT8rr, OUT16rr, OUT32rr)>;
|
|
|
|
def AtomWrite01_70 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 70;
|
|
let ResourceCycles = [70];
|
|
}
|
|
def : InstRW<[AtomWrite01_70], (instrs DIVPSrr, DIVPSrm, SQRTPSr, SQRTPSm)>;
|
|
|
|
def AtomWrite01_71 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 71;
|
|
let ResourceCycles = [71];
|
|
}
|
|
def : InstRW<[AtomWrite01_71], (instrs FPREM1,
|
|
INVLPG, INVLPGA32, INVLPGA64)>;
|
|
def : InstRW<[AtomWrite01_71], (instregex "SQRT_F")>;
|
|
|
|
def AtomWrite01_72 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 72;
|
|
let ResourceCycles = [72];
|
|
}
|
|
def : InstRW<[AtomWrite01_72], (instrs OUT8ir, OUT16ir, OUT32ir)>;
|
|
|
|
def AtomWrite01_74 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 74;
|
|
let ResourceCycles = [74];
|
|
}
|
|
def : InstRW<[AtomWrite01_74], (instrs OUTSB, OUTSL, OUTSW)>;
|
|
|
|
def AtomWrite01_77 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 77;
|
|
let ResourceCycles = [77];
|
|
}
|
|
def : InstRW<[AtomWrite01_77], (instrs FSCALE)>;
|
|
|
|
def AtomWrite01_78 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 78;
|
|
let ResourceCycles = [78];
|
|
}
|
|
def : InstRW<[AtomWrite01_78], (instrs RDMSR)>;
|
|
|
|
def AtomWrite01_79 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 79;
|
|
let ResourceCycles = [79];
|
|
}
|
|
def : InstRW<[AtomWrite01_79], (instregex "RET(L|Q|W)?$",
|
|
"LRETI?(L|Q|W)")>;
|
|
|
|
def AtomWrite01_92 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 92;
|
|
let ResourceCycles = [92];
|
|
}
|
|
def : InstRW<[AtomWrite01_92], (instrs IN8ri, IN16ri, IN32ri)>;
|
|
|
|
def AtomWrite01_94 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 94;
|
|
let ResourceCycles = [94];
|
|
}
|
|
def : InstRW<[AtomWrite01_94], (instrs IN8rr, IN16rr, IN32rr)>;
|
|
|
|
def AtomWrite01_99 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 99;
|
|
let ResourceCycles = [99];
|
|
}
|
|
def : InstRW<[AtomWrite01_99], (instrs F2XM1)>;
|
|
|
|
def AtomWrite01_121 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 121;
|
|
let ResourceCycles = [121];
|
|
}
|
|
def : InstRW<[AtomWrite01_121], (instrs CPUID)>;
|
|
|
|
def AtomWrite01_125 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 125;
|
|
let ResourceCycles = [125];
|
|
}
|
|
def : InstRW<[AtomWrite01_125], (instrs DIVPDrr, DIVPDrm, SQRTPDr, SQRTPDm)>;
|
|
|
|
def AtomWrite01_127 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 127;
|
|
let ResourceCycles = [127];
|
|
}
|
|
def : InstRW<[AtomWrite01_127], (instrs INT)>;
|
|
|
|
def AtomWrite01_130 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 130;
|
|
let ResourceCycles = [130];
|
|
}
|
|
def : InstRW<[AtomWrite01_130], (instrs INT3)>;
|
|
|
|
def AtomWrite01_140 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 140;
|
|
let ResourceCycles = [140];
|
|
}
|
|
def : InstRW<[AtomWrite01_140], (instrs FXSAVE, FXSAVE64)>;
|
|
|
|
def AtomWrite01_141 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 141;
|
|
let ResourceCycles = [141];
|
|
}
|
|
def : InstRW<[AtomWrite01_141], (instrs FXRSTOR, FXRSTOR64)>;
|
|
|
|
def AtomWrite01_146 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 146;
|
|
let ResourceCycles = [146];
|
|
}
|
|
def : InstRW<[AtomWrite01_146], (instrs FYL2X)>;
|
|
|
|
def AtomWrite01_147 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 147;
|
|
let ResourceCycles = [147];
|
|
}
|
|
def : InstRW<[AtomWrite01_147], (instrs FYL2XP1)>;
|
|
|
|
def AtomWrite01_168 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 168;
|
|
let ResourceCycles = [168];
|
|
}
|
|
def : InstRW<[AtomWrite01_168], (instrs FPTAN)>;
|
|
|
|
def AtomWrite01_174 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 174;
|
|
let ResourceCycles = [174];
|
|
}
|
|
def : InstRW<[AtomWrite01_174], (instrs FSINCOS)>;
|
|
def : InstRW<[AtomWrite01_174], (instregex "(COS|SIN)_F")>;
|
|
|
|
def AtomWrite01_183 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 183;
|
|
let ResourceCycles = [183];
|
|
}
|
|
def : InstRW<[AtomWrite01_183], (instrs FPATAN)>;
|
|
|
|
def AtomWrite01_202 : SchedWriteRes<[AtomPort01]> {
|
|
let Latency = 202;
|
|
let ResourceCycles = [202];
|
|
}
|
|
def : InstRW<[AtomWrite01_202], (instrs WRMSR)>;
|
|
|
|
} // SchedModel
|