Andrew Trick 65153639f8 misched interface: Expose the MachineScheduler pass. ... Allow targets to provide their own schedulers (subclass of ScheduleDAGInstrs) to the misched pass. Select schedulers using -misched=... llvm-svn: 152278		2012-03-08 01:41:12 +00:00
..
Analysis	No functionality change. Type::isSized() can be expensive, so avoid calling it	2012-03-07 02:27:53 +00:00
Archive	Avoid using an invalidated iterator.	2012-01-23 05:07:16 +00:00
AsmParser	Convert assert(0) to llvm_unreachable	2012-02-07 05:05:23 +00:00
Bitcode	BitstreamWriter: Change primary output buffer to be a SmallVector instead of an	2012-02-29 20:31:09 +00:00
CodeGen	misched interface: Expose the MachineScheduler pass.	2012-03-08 01:41:12 +00:00
DebugInfo	More dead code removal (using -Wunreachable-code)	2012-01-20 21:51:11 +00:00
ExecutionEngine	Improved support in RuntimeDyldMachO for generating	2012-03-07 23:05:25 +00:00
Linker	Include cctype for isdigit. Patch by Stephen Hines.	2012-03-03 09:36:58 +00:00
MC	Make MCRegisterInfo available to the the MCInstPrinter.	2012-03-05 19:33:20 +00:00
Object	[Object]	2012-03-01 22:19:54 +00:00
Support	Copy the right amount of elements.	2012-03-07 22:48:42 +00:00
TableGen	Fix infinite loop in nested multiclasses.	2012-03-07 16:39:35 +00:00
Target	ARM don't use MCRelaxAll, as it's not safe on ARM.	2012-03-08 00:07:52 +00:00
Transforms	fix typos	2012-03-05 17:39:47 +00:00
VMCore	Switch this code to use hash_combine_range rather than incremental calls	2012-03-07 03:22:32 +00:00
CMakeLists.txt	Move TableGen's parser and entry point into a library	2011-10-01 16:41:13 +00:00
LLVMBuild.txt	LLVMBuild: Introduce a common section which currently has a list of the	2011-12-12 22:45:54 +00:00
Makefile	Remove more of llvmc and dependencies.	2011-09-20 00:34:27 +00:00