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a27dc5bdab
This would fail before because 1x vectors aren't legal, so instead just use the scalar type. Avoids regressions in a future AMDGPU commit to add v4i16/v4f16 as legal types. Test update is just the one test that this triggers on in tree now. It wasn't checking anything before. The result is completely changed since the selects are eliminated. Not sure if it's considered better or not. llvm-svn: 334440
24 lines
903 B
LLVM
24 lines
903 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=armv7-none-linux-gnueabi < %s | FileCheck %s
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define <3 x i64> @shuffle(i1 %dec1, i1 %dec0, <3 x i64> %b) {
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; CHECK-LABEL: shuffle:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: tst r1, #1
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; CHECK-NEXT: moveq r1, #0
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; CHECK-NEXT: vmoveq d16, r1, r1
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; CHECK-NEXT: vldrne d16, [sp]
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; CHECK-NEXT: tst r2, #1
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; CHECK-NEXT: moveq r1, #0
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; CHECK-NEXT: vmoveq d18, r1, r1
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; CHECK-NEXT: vldrne d18, [sp, #8]
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; CHECK-NEXT: vorr d17, d18, d18
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; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
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; CHECK-NEXT: bx lr
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entry:
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%.sink = select i1 %dec1, <3 x i64> %b, <3 x i64> zeroinitializer
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%.sink15 = select i1 %dec0, <3 x i64> %b, <3 x i64> zeroinitializer
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%vecinit7 = shufflevector <3 x i64> %.sink, <3 x i64> %.sink15, <3 x i32> <i32 0, i32 4, i32 undef>
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ret <3 x i64> %vecinit7
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}
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