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83152a3449
Similar to 78d8a821e23e but for ARM, this handles any_extend whilst creating MULL nodes, treating them as zextends. Differential Revision: https://reviews.llvm.org/D93834
289 lines
9.8 KiB
LLVM
289 lines
9.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=armv7a-eabi -mattr=+neon -float-abi=hard %s -o - | FileCheck %s
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define <8 x i8> @vmlai8(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C) nounwind {
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; CHECK-LABEL: vmlai8:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vmla.i8 d0, d1, d2
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; CHECK-NEXT: bx lr
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%tmp4 = mul <8 x i8> %B, %C
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%tmp5 = add <8 x i8> %A, %tmp4
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ret <8 x i8> %tmp5
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}
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define <4 x i16> @vmlai16(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C) nounwind {
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; CHECK-LABEL: vmlai16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vmla.i16 d0, d1, d2
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; CHECK-NEXT: bx lr
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%tmp4 = mul <4 x i16> %B, %C
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%tmp5 = add <4 x i16> %A, %tmp4
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ret <4 x i16> %tmp5
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}
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define <2 x i32> @vmlai32(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C) nounwind {
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; CHECK-LABEL: vmlai32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vmla.i32 d0, d1, d2
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; CHECK-NEXT: bx lr
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%tmp4 = mul <2 x i32> %B, %C
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%tmp5 = add <2 x i32> %A, %tmp4
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ret <2 x i32> %tmp5
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}
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define <2 x float> @vmlaf32(<2 x float> %A, <2 x float> %B, <2 x float> %C) nounwind {
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; CHECK-LABEL: vmlaf32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vmla.f32 d0, d1, d2
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; CHECK-NEXT: bx lr
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%tmp4 = fmul <2 x float> %B, %C
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%tmp5 = fadd <2 x float> %A, %tmp4
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ret <2 x float> %tmp5
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}
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define <16 x i8> @vmlaQi8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C) nounwind {
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; CHECK-LABEL: vmlaQi8:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vmla.i8 q0, q1, q2
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; CHECK-NEXT: bx lr
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%tmp4 = mul <16 x i8> %B, %C
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%tmp5 = add <16 x i8> %A, %tmp4
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ret <16 x i8> %tmp5
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}
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define <8 x i16> @vmlaQi16(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C) nounwind {
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; CHECK-LABEL: vmlaQi16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vmla.i16 q0, q1, q2
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; CHECK-NEXT: bx lr
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%tmp4 = mul <8 x i16> %B, %C
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%tmp5 = add <8 x i16> %A, %tmp4
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ret <8 x i16> %tmp5
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}
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define <4 x i32> @vmlaQi32(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) nounwind {
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; CHECK-LABEL: vmlaQi32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vmla.i32 q0, q1, q2
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; CHECK-NEXT: bx lr
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%tmp4 = mul <4 x i32> %B, %C
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%tmp5 = add <4 x i32> %A, %tmp4
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ret <4 x i32> %tmp5
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}
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define <4 x float> @vmlaQf32(<4 x float> %A, <4 x float> %B, <4 x float> %C) nounwind {
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; CHECK-LABEL: vmlaQf32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vmla.f32 q0, q1, q2
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; CHECK-NEXT: bx lr
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%tmp4 = fmul <4 x float> %B, %C
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%tmp5 = fadd <4 x float> %A, %tmp4
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ret <4 x float> %tmp5
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}
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define <8 x i16> @vmlals8(<8 x i16> %A, <8 x i8> %B, <8 x i8> %C) nounwind {
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; CHECK-LABEL: vmlals8:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vmlal.s8 q0, d2, d3
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; CHECK-NEXT: bx lr
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%tmp4 = sext <8 x i8> %B to <8 x i16>
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%tmp5 = sext <8 x i8> %C to <8 x i16>
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%tmp6 = mul <8 x i16> %tmp4, %tmp5
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%tmp7 = add <8 x i16> %A, %tmp6
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ret <8 x i16> %tmp7
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}
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define <4 x i32> @vmlals16(<4 x i32> %A, <4 x i16> %B, <4 x i16> %C) nounwind {
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; CHECK-LABEL: vmlals16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vmlal.s16 q0, d2, d3
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; CHECK-NEXT: bx lr
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%tmp4 = sext <4 x i16> %B to <4 x i32>
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%tmp5 = sext <4 x i16> %C to <4 x i32>
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%tmp6 = mul <4 x i32> %tmp4, %tmp5
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%tmp7 = add <4 x i32> %A, %tmp6
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ret <4 x i32> %tmp7
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}
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define <2 x i64> @vmlals32(<2 x i64> %A, <2 x i32> %B, <2 x i32> %C) nounwind {
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; CHECK-LABEL: vmlals32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vmlal.s32 q0, d2, d3
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; CHECK-NEXT: bx lr
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%tmp4 = sext <2 x i32> %B to <2 x i64>
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%tmp5 = sext <2 x i32> %C to <2 x i64>
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%tmp6 = mul <2 x i64> %tmp4, %tmp5
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%tmp7 = add <2 x i64> %A, %tmp6
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ret <2 x i64> %tmp7
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}
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define <8 x i16> @vmlalu8(<8 x i16> %A, <8 x i8> %B, <8 x i8> %C) nounwind {
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; CHECK-LABEL: vmlalu8:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vmlal.u8 q0, d2, d3
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; CHECK-NEXT: bx lr
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%tmp4 = zext <8 x i8> %B to <8 x i16>
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%tmp5 = zext <8 x i8> %C to <8 x i16>
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%tmp6 = mul <8 x i16> %tmp4, %tmp5
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%tmp7 = add <8 x i16> %A, %tmp6
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ret <8 x i16> %tmp7
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}
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define <4 x i32> @vmlalu16(<4 x i32> %A, <4 x i16> %B, <4 x i16> %C) nounwind {
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; CHECK-LABEL: vmlalu16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vmlal.u16 q0, d2, d3
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; CHECK-NEXT: bx lr
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%tmp4 = zext <4 x i16> %B to <4 x i32>
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%tmp5 = zext <4 x i16> %C to <4 x i32>
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%tmp6 = mul <4 x i32> %tmp4, %tmp5
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%tmp7 = add <4 x i32> %A, %tmp6
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ret <4 x i32> %tmp7
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}
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define <2 x i64> @vmlalu32(<2 x i64> %A, <2 x i32> %B, <2 x i32> %C) nounwind {
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; CHECK-LABEL: vmlalu32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vmlal.u32 q0, d2, d3
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; CHECK-NEXT: bx lr
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%tmp4 = zext <2 x i32> %B to <2 x i64>
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%tmp5 = zext <2 x i32> %C to <2 x i64>
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%tmp6 = mul <2 x i64> %tmp4, %tmp5
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%tmp7 = add <2 x i64> %A, %tmp6
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ret <2 x i64> %tmp7
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}
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define <8 x i16> @vmlala8(<8 x i16> %A, <8 x i8> %B, <8 x i8> %C) nounwind {
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; CHECK-LABEL: vmlala8:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vmlal.u8 q0, d2, d3
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; CHECK-NEXT: vbic.i16 q0, #0xff00
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; CHECK-NEXT: bx lr
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%tmp4 = zext <8 x i8> %B to <8 x i16>
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%tmp5 = zext <8 x i8> %C to <8 x i16>
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%tmp6 = mul <8 x i16> %tmp4, %tmp5
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%tmp7 = add <8 x i16> %A, %tmp6
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%and = and <8 x i16> %tmp7, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
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ret <8 x i16> %and
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}
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define <4 x i32> @vmlala16(<4 x i32> %A, <4 x i16> %B, <4 x i16> %C) nounwind {
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; CHECK-LABEL: vmlala16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vmlal.u16 q0, d2, d3
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; CHECK-NEXT: vmov.i32 q8, #0xffff
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; CHECK-NEXT: vand q0, q0, q8
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; CHECK-NEXT: bx lr
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%tmp4 = zext <4 x i16> %B to <4 x i32>
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%tmp5 = zext <4 x i16> %C to <4 x i32>
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%tmp6 = mul <4 x i32> %tmp4, %tmp5
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%tmp7 = add <4 x i32> %A, %tmp6
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%and = and <4 x i32> %tmp7, <i32 65535, i32 65535, i32 65535, i32 65535>
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ret <4 x i32> %and
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}
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define <2 x i64> @vmlala32(<2 x i64> %A, <2 x i32> %B, <2 x i32> %C) nounwind {
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; CHECK-LABEL: vmlala32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vmlal.u32 q0, d2, d3
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; CHECK-NEXT: vmov.i64 q8, #0xffffffff
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; CHECK-NEXT: vand q0, q0, q8
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; CHECK-NEXT: bx lr
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%tmp4 = zext <2 x i32> %B to <2 x i64>
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%tmp5 = zext <2 x i32> %C to <2 x i64>
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%tmp6 = mul <2 x i64> %tmp4, %tmp5
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%tmp7 = add <2 x i64> %A, %tmp6
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%and = and <2 x i64> %tmp7, <i64 4294967295, i64 4294967295>
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ret <2 x i64> %and
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}
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define arm_aapcs_vfpcc <4 x i32> @test_vmlal_lanes16(<4 x i32> %arg0_int32x4_t, <4 x i16> %arg1_int16x4_t, <4 x i16> %arg2_int16x4_t) nounwind readnone {
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; CHECK-LABEL: test_vmlal_lanes16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmlal.s16 q0, d2, d3[1]
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; CHECK-NEXT: bx lr
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entry:
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%0 = shufflevector <4 x i16> %arg2_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
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%1 = sext <4 x i16> %arg1_int16x4_t to <4 x i32>
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%2 = sext <4 x i16> %0 to <4 x i32>
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%3 = mul <4 x i32> %1, %2
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%4 = add <4 x i32> %arg0_int32x4_t, %3
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ret <4 x i32> %4
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}
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define arm_aapcs_vfpcc <2 x i64> @test_vmlal_lanes32(<2 x i64> %arg0_int64x2_t, <2 x i32> %arg1_int32x2_t, <2 x i32> %arg2_int32x2_t) nounwind readnone {
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; CHECK-LABEL: test_vmlal_lanes32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmlal.s32 q0, d2, d3[1]
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; CHECK-NEXT: bx lr
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entry:
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%0 = shufflevector <2 x i32> %arg2_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
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%1 = sext <2 x i32> %arg1_int32x2_t to <2 x i64>
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%2 = sext <2 x i32> %0 to <2 x i64>
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%3 = mul <2 x i64> %1, %2
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%4 = add <2 x i64> %arg0_int64x2_t, %3
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ret <2 x i64> %4
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}
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define arm_aapcs_vfpcc <4 x i32> @test_vmlal_laneu16(<4 x i32> %arg0_uint32x4_t, <4 x i16> %arg1_uint16x4_t, <4 x i16> %arg2_uint16x4_t) nounwind readnone {
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; CHECK-LABEL: test_vmlal_laneu16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmlal.u16 q0, d2, d3[1]
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; CHECK-NEXT: bx lr
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entry:
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%0 = shufflevector <4 x i16> %arg2_uint16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
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%1 = zext <4 x i16> %arg1_uint16x4_t to <4 x i32>
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%2 = zext <4 x i16> %0 to <4 x i32>
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%3 = mul <4 x i32> %1, %2
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%4 = add <4 x i32> %arg0_uint32x4_t, %3
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ret <4 x i32> %4
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}
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define arm_aapcs_vfpcc <2 x i64> @test_vmlal_laneu32(<2 x i64> %arg0_uint64x2_t, <2 x i32> %arg1_uint32x2_t, <2 x i32> %arg2_uint32x2_t) nounwind readnone {
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; CHECK-LABEL: test_vmlal_laneu32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmlal.u32 q0, d2, d3[1]
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; CHECK-NEXT: bx lr
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entry:
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%0 = shufflevector <2 x i32> %arg2_uint32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
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%1 = zext <2 x i32> %arg1_uint32x2_t to <2 x i64>
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%2 = zext <2 x i32> %0 to <2 x i64>
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%3 = mul <2 x i64> %1, %2
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%4 = add <2 x i64> %arg0_uint64x2_t, %3
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ret <2 x i64> %4
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}
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define arm_aapcs_vfpcc <4 x i32> @test_vmlal_lanea16(<4 x i32> %arg0_uint32x4_t, <4 x i16> %arg1_uint16x4_t, <4 x i16> %arg2_uint16x4_t) nounwind readnone {
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; CHECK-LABEL: test_vmlal_lanea16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmlal.u16 q0, d2, d3[1]
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; CHECK-NEXT: vmov.i32 q8, #0xffff
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; CHECK-NEXT: vand q0, q0, q8
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; CHECK-NEXT: bx lr
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entry:
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%0 = shufflevector <4 x i16> %arg2_uint16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
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%1 = zext <4 x i16> %arg1_uint16x4_t to <4 x i32>
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%2 = zext <4 x i16> %0 to <4 x i32>
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%3 = mul <4 x i32> %1, %2
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%4 = add <4 x i32> %arg0_uint32x4_t, %3
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%and = and <4 x i32> %4, <i32 65535, i32 65535, i32 65535, i32 65535>
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ret <4 x i32> %and
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}
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define arm_aapcs_vfpcc <2 x i64> @test_vmlal_lanea32(<2 x i64> %arg0_uint64x2_t, <2 x i32> %arg1_uint32x2_t, <2 x i32> %arg2_uint32x2_t) nounwind readnone {
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; CHECK-LABEL: test_vmlal_lanea32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmlal.u32 q0, d2, d3[1]
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; CHECK-NEXT: vmov.i64 q8, #0xffffffff
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; CHECK-NEXT: vand q0, q0, q8
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; CHECK-NEXT: bx lr
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entry:
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%0 = shufflevector <2 x i32> %arg2_uint32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
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%1 = zext <2 x i32> %arg1_uint32x2_t to <2 x i64>
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%2 = zext <2 x i32> %0 to <2 x i64>
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%3 = mul <2 x i64> %1, %2
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%4 = add <2 x i64> %arg0_uint64x2_t, %3
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%and = and <2 x i64> %4, <i64 4294967295, i64 4294967295>
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ret <2 x i64> %and
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}
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