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36d0cb3fd9
This matches GCC and MSVC's behaviour, and saves on code size. We were already not extending i1 return values on x86_64 after r127766. This takes that patch further by applying it to x86 target as well, and also for i8 and i16. The ABI docs have been unclear about the required behaviour here. The new i386 psABI [1] clearly states (Table 2.4, page 14) that i1, i8, and i16 return vales do not need to be extended beyond 8 bits. The x86_64 ABI doc is being updated to say the same [2]. Differential Revision: http://reviews.llvm.org/D16907 [1]. https://01.org/sites/default/files/file_attach/intel386-psabi-1.0.pdf [2]. https://groups.google.com/d/msg/x86-64-abi/E8O33onbnGQ/_RFWw_ixDQAJ llvm-svn: 260133
97 lines
2.8 KiB
LLVM
97 lines
2.8 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin -asm-verbose=false | FileCheck %s -check-prefix=64BIT
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; rdar://7329206
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; In 32-bit the partial register stall would degrade performance.
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define zeroext i16 @t1(i16 zeroext %c, i16 zeroext %k) nounwind ssp {
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entry:
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; 32BIT-LABEL: t1:
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; 32BIT: movw 20(%esp), %ax
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; 32BIT-NOT: movw %ax, %cx
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; 32BIT: leal 1(%eax), %ecx
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; 64BIT-LABEL: t1:
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; 64BIT-NOT: movw %si, %ax
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; 64BIT: leal 1(%rsi), %ebx
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%0 = icmp eq i16 %k, %c ; <i1> [#uses=1]
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%1 = add i16 %k, 1 ; <i16> [#uses=3]
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br i1 %0, label %bb, label %bb1
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bb: ; preds = %entry
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tail call void @foo(i16 zeroext %1) nounwind
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ret i16 %1
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bb1: ; preds = %entry
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ret i16 %1
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}
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define zeroext i16 @t2(i16 zeroext %c, i16 zeroext %k) nounwind ssp {
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entry:
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; 32BIT-LABEL: t2:
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; 32BIT: movw 20(%esp), %ax
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; 32BIT-NOT: movw %ax, %cx
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; 32BIT: leal -1(%eax), %ecx
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; 64BIT-LABEL: t2:
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; 64BIT-NOT: movw %si, %ax
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; 64BIT: leal -1(%rsi), %ebx
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; 64BIT: movzwl %bx
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%0 = icmp eq i16 %k, %c ; <i1> [#uses=1]
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%1 = add i16 %k, -1 ; <i16> [#uses=3]
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br i1 %0, label %bb, label %bb1
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bb: ; preds = %entry
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tail call void @foo(i16 zeroext %1) nounwind
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ret i16 %1
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bb1: ; preds = %entry
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ret i16 %1
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}
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declare void @foo(i16 zeroext)
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define zeroext i16 @t3(i16 zeroext %c, i16 zeroext %k) nounwind ssp {
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entry:
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; 32BIT-LABEL: t3:
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; 32BIT: movw 20(%esp), %ax
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; 32BIT-NOT: movw %ax, %cx
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; 32BIT: leal 2(%eax), %ecx
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; 64BIT-LABEL: t3:
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; 64BIT-NOT: movw %si, %ax
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; 64BIT: leal 2(%rsi), %ebx
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%0 = add i16 %k, 2 ; <i16> [#uses=3]
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%1 = icmp eq i16 %k, %c ; <i1> [#uses=1]
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br i1 %1, label %bb, label %bb1
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bb: ; preds = %entry
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tail call void @foo(i16 zeroext %0) nounwind
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ret i16 %0
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bb1: ; preds = %entry
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ret i16 %0
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}
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define zeroext i16 @t4(i16 zeroext %c, i16 zeroext %k) nounwind ssp {
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entry:
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; 32BIT-LABEL: t4:
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; 32BIT: movw 16(%esp), %ax
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; 32BIT: movw 20(%esp), %cx
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; 32BIT-NOT: movw %cx, %dx
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; 32BIT: leal (%ecx,%eax), %edx
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; 64BIT-LABEL: t4:
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; 64BIT-NOT: movw %si, %ax
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; 64BIT: leal (%rsi,%rdi), %ebx
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%0 = add i16 %k, %c ; <i16> [#uses=3]
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%1 = icmp eq i16 %k, %c ; <i1> [#uses=1]
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br i1 %1, label %bb, label %bb1
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bb: ; preds = %entry
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tail call void @foo(i16 zeroext %0) nounwind
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ret i16 %0
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bb1: ; preds = %entry
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ret i16 %0
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}
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