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c21c095194
This commit modifies the way the machine basic blocks are serialized - now the
machine basic blocks are serialized using a custom syntax instead of relying on
YAML primitives. Instead of using YAML mappings to represent the individual
machine basic blocks in a machine function's body, the new syntax uses a single
YAML block scalar which contains all of the machine basic blocks and
instructions for that function.
This is an example of a function's body that uses the old syntax:
body:
- id: 0
name: entry
instructions:
- '%eax = MOV32r0 implicit-def %eflags'
- 'RETQ %eax'
...
The same body is now written like this:
body: |
bb.0.entry:
%eax = MOV32r0 implicit-def %eflags
RETQ %eax
...
This syntax change is motivated by the fact that the bundled machine
instructions didn't map that well to the old syntax which was using a single
YAML sequence to store all of the machine instructions in a block. The bundled
machine instructions internally use flags like BundledPred and BundledSucc to
determine the bundles, and serializing them as MI flags using the old syntax
would have had a negative impact on the readability and the ease of editing
for MIR files. The new syntax allows me to serialize the bundled machine
instructions using a block construct without relying on the internal flags,
for example:
BUNDLE implicit-def dead %itstate, implicit-def %s1 ... {
t2IT 1, 24, implicit-def %itstate
%s1 = VMOVS killed %s0, 1, killed %cpsr, implicit killed %itstate
}
This commit also converts the MIR testcases to the new syntax. I developed
a script that can convert from the old syntax to the new one. I will post the
script on the llvm-commits mailing list in the thread for this commit.
llvm-svn: 244982
37 lines
1.0 KiB
YAML
37 lines
1.0 KiB
YAML
# RUN: llc -run-pass postrapseudos -mtriple=x86_64-unknown-unknown -mattr=+3dnow -o /dev/null %s | FileCheck %s
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# This test verifies that the ExpandPostRA pass expands the GR64 <-> VR64
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# copies into appropriate MMX_MOV instructions.
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--- |
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define <2 x i32> @test_pswapdsi(<2 x i32> %a) nounwind readnone {
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entry:
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%0 = bitcast <2 x i32> %a to x86_mmx
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%1 = tail call x86_mmx @llvm.x86.3dnowa.pswapd(x86_mmx %0)
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%2 = bitcast x86_mmx %1 to <2 x i32>
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ret <2 x i32> %2
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}
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declare x86_mmx @llvm.x86.3dnowa.pswapd(x86_mmx) nounwind readnone
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...
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---
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name: test_pswapdsi
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: %xmm0
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%xmm0 = PSHUFDri killed %xmm0, -24
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MOVPQI2QImr %rsp, 1, _, -8, _, killed %xmm0
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%mm0 = PSWAPDrm %rsp, 1, _, -8, _
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; CHECK: %rax = MMX_MOVD64from64rr %mm0
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; CHECK-NEXT: %mm0 = MMX_MOVD64to64rr %rax
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%rax = COPY %mm0
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%mm0 = COPY %rax
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MMX_MOVQ64mr %rsp, 1, _, -16, _, killed %mm0
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%xmm0 = MOVQI2PQIrm %rsp, 1, _, -16, _
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%xmm0 = PSHUFDri killed %xmm0, -44
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RETQ %xmm0
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...
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