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5698ba2abd
Added support for the extraction of the upper 128-bit subvectors for lower/upper half undef shuffles if it would reduce the number of extractions/insertions or avoid loads of AVX2 permps/permd shuffle masks. Minor follow up to D15477. llvm-svn: 258000
27 lines
1.2 KiB
LLVM
27 lines
1.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s
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; Avoid unnecessary vinsertf128
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define <4 x i64> @test1(<4 x i64> %a) nounwind {
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; CHECK-LABEL: test1:
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; CHECK: # BB#0:
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; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm1
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; CHECK-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
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; CHECK-NEXT: retl
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%b = shufflevector <4 x i64> %a, <4 x i64> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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ret <4 x i64>%b
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}
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define <8 x i16> @test2(<4 x i16>* %v) nounwind {
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; CHECK-LABEL: test2:
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; CHECK: # BB#0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
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; CHECK-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
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; CHECK-NEXT: retl
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%v9 = load <4 x i16>, <4 x i16> * %v, align 8
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%v10 = shufflevector <4 x i16> %v9, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
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%v11 = shufflevector <8 x i16> <i16 undef, i16 undef, i16 undef, i16 undef, i16 0, i16 0, i16 0, i16 0>, <8 x i16> %v10, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7>
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ret <8 x i16> %v11
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}
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