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d5eac4bb77
As shown in: https://llvm.org/bugs/show_bug.cgi?id=23203 ...we currently die because lowering believes that mfence is allowed without SSE2 on x86-64, but the instruction def doesn't know that. I don't know if allowing mfence without SSE is right, but if not, at least now it's consistently wrong. :) Differential Revision: http://reviews.llvm.org/D17219 llvm-svn: 260828
38 lines
956 B
LLVM
38 lines
956 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X32
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-sse2 | FileCheck %s --check-prefix=X64
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; It doesn't matter if an x86-64 target has specified "no-sse2"; we still can use mfence.
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define void @test() {
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; X32-LABEL: test:
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; X32: # BB#0:
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; X32-NEXT: mfence
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; X32-NEXT: retl
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;
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; X64-LABEL: test:
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; X64: # BB#0:
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; X64-NEXT: mfence
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; X64-NEXT: retq
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fence seq_cst
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ret void
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}
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define i32 @fence(i32* %ptr) {
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; X32-LABEL: fence:
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; X32: # BB#0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: mfence
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; X32-NEXT: movl (%eax), %eax
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; X32-NEXT: retl
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;
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; X64-LABEL: fence:
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; X64: # BB#0:
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; X64-NEXT: mfence
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; X64-NEXT: movl (%rdi), %eax
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; X64-NEXT: retq
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%atomic = atomicrmw add i32* %ptr, i32 0 seq_cst
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ret i32 %atomic
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}
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