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41b71f19a3
The AArch64 test was broken since the result register already had a set register class, so this test was a no-op. The mapping verify call would fail because the result size is not the same as the inputs like in a copy or phi. The AMDGPU testcases are half broken and introduce illegal VGPR->SGPR copies which need much more work to handle correctly (same for phis), but add them as a baseline. llvm-svn: 356713
23 lines
611 B
YAML
23 lines
611 B
YAML
# RUN: llc %s -mtriple aarch64-- -o - -run-pass regbankselect | FileCheck %s
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---
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# CHECK-LABEL: foo
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# Check that we produce a valid mapping for REG_SEQUENCE.
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# This used to fail the RegisterBankInfo verify because
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# we were using the exclusively the type of the definition
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# whereas since REG_SEQUENCE are kind of target opcode
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# their definition may not have a type.
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#
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# CHECK: %0:fpr(s128) = REG_SEQUENCE $d0, %subreg.dsub0, $d1, %subreg.dsub1
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name: foo
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0, $d1
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%0:_(s128) = REG_SEQUENCE $d0, %subreg.dsub0, $d1, %subreg.dsub1
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...
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