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65613836e9
cases where we have partial integer loads and stores to an otherwise
promotable alloca to widen[1] those loads and stores to cover the entire
alloca and bitcast them into the appropriate type such that promotion
can proceed.
These partial loads and stores stem from an annoying confluence of ARM's
calling convention and ABI lowering and the FCA pre-splitting which
takes place in SROA. Clang lowers a { double, double } in-register
function argument as a [4 x i32] function argument to ensure it is
placed into integer 32-bit registers (a really unnerving implicit
contract between Clang and the ARM backend I would add). This results in
a FCA load of [4 x i32]* from the { double, double } alloca, and SROA
decomposes this into a sequence of i32 loads and stores. Inlining
proceeds, code gets folded, but at the end of the day, we still have i32
stores to the low and high halves of a double alloca. Widening these to
be i64 operations, and bitcasting them to double prior to loading or
storing allows promotion to proceed for these allocas.
I looked quite a bit changing the IR which Clang produces for this case
to be more friendly, but small changes seem unlikely to help. I think
the best representation we could use currently would be to pass 4 i32
arguments thereby avoiding any FCAs, but that would still require this
fix. It seems like it might eventually be nice to somehow encode the ABI
register selection choices outside of the parameter type system so that
the parameter can be a { double, double }, but the CC register
annotations indicate that this should be passed via 4 integer registers.
This patch does not address the second problem in PR14059, which is the
reverse: when a struct alloca is loaded as a *larger* single integer.
This patch also does not address some of the code quality issues with
the FCA-splitting. Those don't actually impede any optimizations really,
but they're on my list to clean up.
[1]: Pedantic footnote: for those concerned about memory model issues
here, this is safe. For the alloca to be promotable, it cannot escape or
have any use of its address that could allow these loads or stores to be
racing. Thus, widening is always safe.
llvm-svn: 165928
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| .. | ||
| ADCE | ||
| ArgumentPromotion | ||
| BBVectorize | ||
| BlockPlacement | ||
| BranchFolding | ||
| CodeExtractor | ||
| CodeGenPrepare | ||
| ConstantMerge | ||
| ConstProp | ||
| CorrelatedValuePropagation | ||
| DeadArgElim | ||
| DeadStoreElimination | ||
| EarlyCSE | ||
| FunctionAttrs | ||
| GlobalDCE | ||
| GlobalOpt | ||
| GVN | ||
| IndVarSimplify | ||
| Inline | ||
| InstCombine | ||
| InstSimplify | ||
| Internalize | ||
| IPConstantProp | ||
| JumpThreading | ||
| LCSSA | ||
| LICM | ||
| LoopDeletion | ||
| LoopIdiom | ||
| LoopRotate | ||
| LoopSimplify | ||
| LoopStrengthReduce | ||
| LoopUnroll | ||
| LoopUnswitch | ||
| LowerAtomic | ||
| LowerExpectIntrinsic | ||
| LowerInvoke | ||
| LowerSwitch | ||
| Mem2Reg | ||
| MemCpyOpt | ||
| MergeFunc | ||
| MetaRenamer | ||
| ObjCARC | ||
| PhaseOrdering | ||
| PruneEH | ||
| Reassociate | ||
| ScalarRepl | ||
| SCCP | ||
| SimplifyCFG | ||
| SimplifyLibCalls | ||
| Sink | ||
| SROA | ||
| StripSymbols | ||
| TailCallElim | ||
| TailDup | ||