mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-24 03:33:20 +01:00
a4f824b0d6
The assertion was checking that the virtual register VReg used to represent the physical register PReg uses the same register class as the one passed to MachineFunction::addLiveIn. This is over-constraining because it is sufficient to check that the register class of VReg (VRegRC) is a subclass of the register class of PReg (PRegRC) and that VRegRC contains PReg. Indeed, if VReg gets constrained because of some operation constraints between two calls of MachineFunction::addLiveIn, the original assertion cannot match. This fixes <rdar://problem/15633429>. llvm-svn: 197097
25 lines
679 B
LLVM
25 lines
679 B
LLVM
; RUN: llc < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
|
|
; Test case related to <rdar://problem/15633429>.
|
|
|
|
; CHECK-LABEL: small
|
|
define i64 @small(i64 %encodedBase) {
|
|
cmp:
|
|
%lnot.i.i = icmp eq i64 %encodedBase, 0
|
|
br i1 %lnot.i.i, label %if, label %else
|
|
if:
|
|
%tmp1 = call i8* @llvm.returnaddress(i32 0)
|
|
br label %end
|
|
else:
|
|
%tmp3 = call i8* @llvm.returnaddress(i32 0)
|
|
%ptr = getelementptr inbounds i8* %tmp3, i64 -16
|
|
%ld = load i8* %ptr, align 4
|
|
%tmp2 = inttoptr i8 %ld to i8*
|
|
br label %end
|
|
end:
|
|
%tmp = phi i8* [ %tmp1, %if ], [ %tmp2, %else ]
|
|
%coerce.val.pi56 = ptrtoint i8* %tmp to i64
|
|
ret i64 %coerce.val.pi56
|
|
}
|
|
|
|
declare i8* @llvm.returnaddress(i32)
|