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6efe5100eb
- check that -mcpu=slm uses the call register indirect optimization - check that -mcpu=slm runs the scheduler - check that -mcpu=slm supports the movbe instruction llvm-svn: 190814
46 lines
1.2 KiB
LLVM
46 lines
1.2 KiB
LLVM
; RUN: llc -mtriple=x86_64-linux -mcpu=atom < %s | FileCheck %s
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; RUN: llc -mtriple=x86_64-linux -mcpu=slm < %s | FileCheck %s -check-prefix=SLM
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declare i32 @llvm.bswap.i32(i32) nounwind readnone
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declare i64 @llvm.bswap.i64(i64) nounwind readnone
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define void @test1(i32* nocapture %x, i32 %y) nounwind {
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%bswap = call i32 @llvm.bswap.i32(i32 %y)
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store i32 %bswap, i32* %x, align 4
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ret void
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; CHECK-LABEL: test1:
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; CHECK: movbel %esi, (%rdi)
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; SLM-LABEL: test1:
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; SLM: movbel %esi, (%rdi)
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}
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define i32 @test2(i32* %x) nounwind {
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%load = load i32* %x, align 4
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%bswap = call i32 @llvm.bswap.i32(i32 %load)
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ret i32 %bswap
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; CHECK-LABEL: test2:
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; CHECK: movbel (%rdi), %eax
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; SLM-LABEL: test2:
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; SLM: movbel (%rdi), %eax
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}
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define void @test3(i64* %x, i64 %y) nounwind {
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%bswap = call i64 @llvm.bswap.i64(i64 %y)
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store i64 %bswap, i64* %x, align 8
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ret void
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; CHECK-LABEL: test3:
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; CHECK: movbeq %rsi, (%rdi)
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; SLM-LABEL: test3:
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; SLM: movbeq %rsi, (%rdi)
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}
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define i64 @test4(i64* %x) nounwind {
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%load = load i64* %x, align 8
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%bswap = call i64 @llvm.bswap.i64(i64 %load)
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ret i64 %bswap
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; CHECK-LABEL: test4:
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; CHECK: movbeq (%rdi), %rax
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; SLM-LABEL: test4:
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; SLM: movbeq (%rdi), %rax
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}
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