Renato Golin eb17383852 Elide repeated register operand in Thumb1 instructions ... This patch makes the ARM backend transform 3 operand instructions such as 'adds/subs' to the 2 operand version of the same instruction if the first two register operands are the same. Example: 'adds r0, r0, #1' will is transformed to 'adds r0, #1'. Currently for some instructions such as 'adds' if you try to assemble 'adds r0, r0, #8' for thumb v6m the assembler would throw an error message because the immediate cannot be encoded using 3 bits. The backend should be smart enough to transform the instruction to 'adds r0, #8', which allows for larger immediate constants. Patch by Ranjeet Singh. llvm-svn: 218521		2014-09-26 16:14:29 +00:00
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AArch64	AArch64: allow constant expressions for shifted reg literals	2014-09-23 22:16:02 +00:00
ARM	Elide repeated register operand in Thumb1 instructions	2014-09-26 16:14:29 +00:00
AsmParser	MC: AsmLexer: handle multi-character CommentStrings correctly	2014-08-14 02:51:43 +00:00
COFF	MC: Use @IMGREL instead of @IMGREL32, which we can't parse	2014-09-25 02:09:18 +00:00
Disassembler	Thumb2 M-class MSR instruction support changes	2014-09-01 11:25:07 +00:00
ELF	Fix typos in comments, NFC	2014-08-29 21:53:01 +00:00
MachO	[dwarfdump] Dump full filenames as DW_AT_(decl|call)_file attribute values	2014-09-22 12:36:04 +00:00
Markup
Mips	[mips] Add assembler support for the .set nodsp directive.	2014-09-17 09:01:54 +00:00
PowerPC	[PowerPC] Add support for dcbtst and icbt (prefetch)	2014-08-23 23:21:04 +00:00
Sparc	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
SystemZ	Exclude known and bugzilled failures from UBSan bootstrap	2014-09-17 20:17:52 +00:00
X86	MC: Use @IMGREL instead of @IMGREL32, which we can't parse	2014-09-25 02:09:18 +00:00