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https://github.com/RPCS3/llvm-mirror.git
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7743098c5d
This patch adds initial support for a DemandedElts mask to the internal computeKnownBits/ComputeNumSignBits methods, matching the SelectionDAG and GlobalISel equivalents. So far only a couple of instructions have been setup to handle the DemandedElts, the remainder still using the existing 'all elements' default. The plan is to extend support as we have test coverage. Differential Revision: https://reviews.llvm.org/D73435
131 lines
3.7 KiB
LLVM
131 lines
3.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -instcombine -S | FileCheck %s
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define i32 @sub1(i32 %x) {
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; CHECK-LABEL: @sub1(
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; CHECK-NEXT: [[Y:%.*]] = sub i32 0, [[X:%.*]]
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; CHECK-NEXT: [[Z:%.*]] = sdiv i32 [[Y]], 337
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; CHECK-NEXT: ret i32 [[Z]]
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;
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%y = sub i32 0, %x
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%z = sdiv i32 %y, 337
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ret i32 %z
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}
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define i32 @sub2(i32 %x) {
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; CHECK-LABEL: @sub2(
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; CHECK-NEXT: [[Z:%.*]] = sdiv i32 [[X:%.*]], -337
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; CHECK-NEXT: ret i32 [[Z]]
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;
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%y = sub nsw i32 0, %x
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%z = sdiv i32 %y, 337
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ret i32 %z
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}
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define i1 @shl_icmp(i64 %X) {
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; CHECK-LABEL: @shl_icmp(
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; CHECK-NEXT: [[B:%.*]] = icmp eq i64 [[X:%.*]], 0
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; CHECK-NEXT: ret i1 [[B]]
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;
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%A = shl nuw i64 %X, 2 ; X/4
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%B = icmp eq i64 %A, 0
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ret i1 %B
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}
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define i64 @shl1(i64 %X, i64* %P) {
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; CHECK-LABEL: @shl1(
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; CHECK-NEXT: [[A:%.*]] = and i64 [[X:%.*]], 312
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; CHECK-NEXT: store i64 [[A]], i64* [[P:%.*]], align 4
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; CHECK-NEXT: [[B:%.*]] = shl nuw nsw i64 [[A]], 8
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; CHECK-NEXT: ret i64 [[B]]
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;
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%A = and i64 %X, 312
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store i64 %A, i64* %P ; multiple uses of A.
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%B = shl i64 %A, 8
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ret i64 %B
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}
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define i32 @preserve1(i32 %x) {
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; CHECK-LABEL: @preserve1(
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; CHECK-NEXT: [[ADD3:%.*]] = add nsw i32 [[X:%.*]], 5
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; CHECK-NEXT: ret i32 [[ADD3]]
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;
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%add = add nsw i32 %x, 2
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%add3 = add nsw i32 %add, 3
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ret i32 %add3
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}
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define i8 @nopreserve1(i8 %x) {
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; CHECK-LABEL: @nopreserve1(
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; CHECK-NEXT: [[ADD3:%.*]] = add i8 [[X:%.*]], -126
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; CHECK-NEXT: ret i8 [[ADD3]]
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;
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%add = add nsw i8 %x, 127
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%add3 = add nsw i8 %add, 3
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ret i8 %add3
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}
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define i8 @nopreserve2(i8 %x) {
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; CHECK-LABEL: @nopreserve2(
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; CHECK-NEXT: [[ADD3:%.*]] = add i8 [[X:%.*]], 3
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; CHECK-NEXT: ret i8 [[ADD3]]
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;
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%add = add i8 %x, 1
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%add3 = add nsw i8 %add, 2
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ret i8 %add3
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}
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define i8 @nopreserve3(i8 %A, i8 %B) {
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; CHECK-LABEL: @nopreserve3(
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; CHECK-NEXT: [[Y:%.*]] = add i8 [[A:%.*]], [[B:%.*]]
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; CHECK-NEXT: [[ADD:%.*]] = add i8 [[Y]], 20
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; CHECK-NEXT: ret i8 [[ADD]]
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;
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%x = add i8 %A, 10
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%y = add i8 %B, 10
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%add = add nsw i8 %x, %y
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ret i8 %add
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}
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define i8 @nopreserve4(i8 %A, i8 %B) {
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; CHECK-LABEL: @nopreserve4(
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; CHECK-NEXT: [[Y:%.*]] = add i8 [[A:%.*]], [[B:%.*]]
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; CHECK-NEXT: [[ADD:%.*]] = add i8 [[Y]], 20
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; CHECK-NEXT: ret i8 [[ADD]]
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;
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%x = add nsw i8 %A, 10
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%y = add nsw i8 %B, 10
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%add = add nsw i8 %x, %y
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ret i8 %add
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}
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define <3 x i32> @shl_nuw_nsw_shuffle_splat_vec(<2 x i8> %x) {
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; CHECK-LABEL: @shl_nuw_nsw_shuffle_splat_vec(
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; CHECK-NEXT: [[T2:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i32>
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; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <2 x i32> [[T2]], <2 x i32> undef, <3 x i32> <i32 1, i32 0, i32 1>
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; CHECK-NEXT: [[T3:%.*]] = shl nuw nsw <3 x i32> [[SHUF]], <i32 17, i32 17, i32 17>
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; CHECK-NEXT: ret <3 x i32> [[T3]]
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;
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%t2 = zext <2 x i8> %x to <2 x i32>
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%shuf = shufflevector <2 x i32> %t2, <2 x i32> undef, <3 x i32> <i32 1, i32 0, i32 1>
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%t3 = shl <3 x i32> %shuf, <i32 17, i32 17, i32 17>
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ret <3 x i32> %t3
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}
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; Negative test - if the shuffle mask contains an undef, we bail out to
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; avoid propagating information that may not be used consistently by callers.
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define <3 x i32> @shl_nuw_nsw_shuffle_undef_elt_splat_vec(<2 x i8> %x) {
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; CHECK-LABEL: @shl_nuw_nsw_shuffle_undef_elt_splat_vec(
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; CHECK-NEXT: [[T2:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i32>
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; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <2 x i32> [[T2]], <2 x i32> undef, <3 x i32> <i32 1, i32 undef, i32 0>
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; CHECK-NEXT: [[T3:%.*]] = shl <3 x i32> [[SHUF]], <i32 17, i32 17, i32 17>
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; CHECK-NEXT: ret <3 x i32> [[T3]]
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;
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%t2 = zext <2 x i8> %x to <2 x i32>
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%shuf = shufflevector <2 x i32> %t2, <2 x i32> undef, <3 x i32> <i32 1, i32 undef, i32 0>
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%t3 = shl <3 x i32> %shuf, <i32 17, i32 17, i32 17>
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ret <3 x i32> %t3
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}
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