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llvm-mirror/lib/Target/AArch64
Mark Murray 31bcffc357 [ARM][AArch64] Add Cortex-A78C Support for Clang and LLVM
This patch upstreams support for the Armv8-a Cortex-A78C
processor for AArch64 and ARM.

In detail:

Adding cortex-a78c as cpu option for aarch64 and arm targets in clang
Adding Cortex-A78C CPU name and ProcessorModel in llvm
Details of the CPU can be found here:
https://www.arm.com/products/silicon-ip-cpu/cortex-a/cortex-a78c
2020-12-29 10:18:59 +00:00
..
AsmParser [AArch64] Add support for ls64 to the .arch_extension asm directive 2020-12-18 15:55:55 +00:00
Disassembler [AArch64] Adding the v8.7-A LD64B/ST64B Accelerator extension 2020-12-17 13:46:23 +00:00
GISel [AArch64][GlobalISel] Notify observer of mutated instruction for shift custom legalization. 2020-12-25 00:31:47 -08:00
MCTargetDesc [AArch64] Add a GPR64x8 register class 2020-12-17 13:45:46 +00:00
TargetInfo llvmbuildectomy - replace llvm-build by plain cmake 2020-11-13 10:35:24 +01:00
Utils [ARM][AArch64] Adding basic support for the v8.7-A architecture 2020-12-17 13:45:08 +00:00
AArch64.h [AArch64][GlobalISel] Introduce a new post-isel optimization pass. 2020-10-23 10:18:36 -07:00
AArch64.td [ARM][AArch64] Add Cortex-A78C Support for Clang and LLVM 2020-12-29 10:18:59 +00:00
AArch64A53Fix835769.cpp
AArch64A57FPLoadBalancing.cpp
AArch64AdvSIMDScalarPass.cpp [AArch64] Update a code comment incorrectly referring to zero_reg. NFC 2020-08-20 14:36:59 +02:00
AArch64AsmPrinter.cpp [llvm][clang][mlir] Add checks for the return values from Target::createXXX to prevent protential null deref 2020-11-21 21:04:12 -08:00
AArch64BranchTargets.cpp [AArch64] PAC/BTI code generation for LLVM generated functions 2020-09-25 11:47:14 +01:00
AArch64CallingConvention.cpp [SVE] Deal with SVE tuple call arguments correctly when running out of registers 2020-11-12 08:41:50 +00:00
AArch64CallingConvention.h
AArch64CallingConvention.td
AArch64CleanupLocalDynamicTLSPass.cpp
AArch64CollectLOH.cpp
AArch64Combine.td [AArch64][GlobalISel] Port some AArch64 target specific MUL combines from SDAG. 2020-11-10 22:21:13 -08:00
AArch64CompressJumpTables.cpp [AArch64] Don't try to compress jump tables if there are any inline asm instructions. 2020-12-10 12:20:02 -08:00
AArch64CondBrTuning.cpp
AArch64ConditionalCompares.cpp
AArch64ConditionOptimizer.cpp
AArch64DeadRegisterDefinitionsPass.cpp
AArch64ExpandImm.cpp
AArch64ExpandImm.h
AArch64ExpandPseudoInsts.cpp Recommit "[AArch64] Lower calls with rv_marker attribute." 2020-12-13 16:20:39 +00:00
AArch64FalkorHWPFFix.cpp Small fixes for "[LoopInfo] empty() -> isInnermost(), add isOutermost()" 2020-09-22 23:59:34 +03:00
AArch64FastISel.cpp [FastISel] update to use intrinsic's isCommutative(); NFC 2020-08-30 11:36:41 -04:00
AArch64FrameLowering.cpp Fix speling in comments. NFC. 2020-11-23 14:43:24 +00:00
AArch64FrameLowering.h [SVE] Return StackOffset for TargetFrameLowering::getFrameIndexReference. 2020-11-05 11:02:18 +00:00
AArch64GenRegisterBankInfo.def
AArch64InstrAtomics.td
AArch64InstrFormats.td [AArch64] Adding the v8.7-A LD64B/ST64B Accelerator extension 2020-12-17 13:46:23 +00:00
AArch64InstrGISel.td [AArch64][GlobalISel] Add AArch64::G_DUPLANE[X] opcodes for lane duplicates. 2020-11-05 11:18:11 -08:00
AArch64InstrInfo.cpp [Target] Use llvm::erase_if (NFC) 2020-12-20 17:43:22 -08:00
AArch64InstrInfo.h [MachineCombiner][NFC] Add MustReduceRegisterPressure goal 2020-12-14 00:02:42 -05:00
AArch64InstrInfo.td [AArch64] Add support for the SPE-EEF feature 2020-12-18 11:11:56 +00:00
AArch64ISelDAGToDAG.cpp [AArch64][SVE] Fix umin/umax lowering to handle out of range imm. 2020-10-23 09:42:56 -07:00
AArch64ISelLowering.cpp [AArch64] Fix legalization of i128 ctpop without neon 2020-12-27 17:24:41 +01:00
AArch64ISelLowering.h [SVE] Lower vector BITREVERSE and BSWAP operations. 2020-12-22 16:49:50 +00:00
AArch64LoadStoreOptimizer.cpp [AArch64] Don't merge sp decrement into later stores when using WinCFI 2020-10-01 19:03:27 +03:00
AArch64MachineFunctionInfo.cpp [AArch64] PAC/BTI code generation for LLVM generated functions 2020-09-25 11:47:14 +01:00
AArch64MachineFunctionInfo.h [MTE] Pin the tagged base pointer to one of the stack slots. 2020-10-15 12:50:16 -07:00
AArch64MacroFusion.cpp
AArch64MacroFusion.h
AArch64MCInstLower.cpp
AArch64MCInstLower.h
AArch64PBQPRegAlloc.cpp
AArch64PBQPRegAlloc.h
AArch64PerfectShuffle.h
AArch64PfmCounters.td
AArch64PromoteConstant.cpp
AArch64RedundantCopyElimination.cpp [AArch64] Fix Copy Elemination for negative values 2020-12-18 13:30:46 +00:00
AArch64RegisterBanks.td
AArch64RegisterInfo.cpp [Target] Use llvm::any_of (NFC) 2020-12-24 19:43:26 -08:00
AArch64RegisterInfo.h [AARCH64][RegisterCoalescer] clang miscompiles zero-extension to long long 2020-09-08 08:04:52 +01:00
AArch64RegisterInfo.td [AArch64] Add a GPR64x8 register class 2020-12-17 13:45:46 +00:00
AArch64SchedA53.td
AArch64SchedA55.td [AArch64] Enable Cortex-A55 schedmodel 2020-11-30 19:28:34 +00:00
AArch64SchedA57.td
AArch64SchedA57WriteRes.td
AArch64SchedCyclone.td
AArch64SchedExynosM3.td
AArch64SchedExynosM4.td
AArch64SchedExynosM5.td
AArch64SchedFalkor.td
AArch64SchedFalkorDetails.td
AArch64SchedKryo.td
AArch64SchedKryoDetails.td
AArch64SchedPredExynos.td
AArch64SchedPredicates.td
AArch64SchedThunderX2T99.td
AArch64SchedThunderX3T110.td
AArch64SchedThunderX.td
AArch64SchedTSV110.td [AArch64] Add pipeline model for HiSilicon's TSV110 2020-11-07 01:23:00 +03:00
AArch64Schedule.td
AArch64SelectionDAGInfo.cpp [CodeGen] Refactor getMemBasePlusOffset & getObjectPtrOffset to accept a TypeSize 2020-08-11 12:17:10 +01:00
AArch64SelectionDAGInfo.h
AArch64SIMDInstrOpt.cpp [AArch64] reuse another map iterator. NFC 2020-09-28 11:30:21 -07:00
AArch64SLSHardening.cpp
AArch64SpeculationHardening.cpp
AArch64StackTagging.cpp Use cast<> instead of dyn_cast<> as we dereference the pointer immediately. NFCI. 2020-10-30 14:33:20 +00:00
AArch64StackTaggingPreRA.cpp [MTE] Pin the tagged base pointer to one of the stack slots. 2020-10-15 12:50:16 -07:00
AArch64StorePairSuppress.cpp
AArch64Subtarget.cpp [ARM][AArch64] Add Cortex-A78C Support for Clang and LLVM 2020-12-29 10:18:59 +00:00
AArch64Subtarget.h [ARM][AArch64] Add Cortex-A78C Support for Clang and LLVM 2020-12-29 10:18:59 +00:00
AArch64SVEInstrInfo.td [SVE] Lower vector BITREVERSE and BSWAP operations. 2020-12-22 16:49:50 +00:00
AArch64SystemOperands.td [AArch64] Add support for the SPE-EEF feature 2020-12-18 11:11:56 +00:00
AArch64TargetMachine.cpp [Triple][MachO] Define "arm64e", an AArch64 subarch for Pointer Auth. 2020-12-03 07:53:59 -08:00
AArch64TargetMachine.h Support addrspacecast initializers with isNoopAddrSpaceCast 2020-07-31 10:42:43 -04:00
AArch64TargetObjectFile.cpp
AArch64TargetObjectFile.h
AArch64TargetTransformInfo.cpp [AArch64][CostModel] Fix cost for mul <2 x i64> 2020-11-30 11:36:55 +00:00
AArch64TargetTransformInfo.h [TTI] Add supportsScalableVectors target hook 2020-12-18 10:37:01 +00:00
CMakeLists.txt llvmbuildectomy - replace llvm-build by plain cmake 2020-11-13 10:35:24 +01:00
SVEInstrFormats.td [SVE] Lower vector BITREVERSE and BSWAP operations. 2020-12-22 16:49:50 +00:00
SVEIntrinsicOpts.cpp [SVE] Fix bug in SVEIntrinsicOpts::optimizePTest 2020-08-14 07:57:21 +01:00