mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-25 20:23:11 +01:00
0ac8aa21f4
This is the second minimal patch keeping Nios2 target buildable. I'm adding subtarget here and other stuff for frame lowering, instruction, register information methods. I do not add any test cases, as still there are missing parts like DAG selector and assembly printing. I plan to include them into the next patch. Patch by Andrei Grischenko <andrei.l.grischenko@intel.com> Differential Revision: https://reviews.llvm.org/D37256 llvm-svn: 313626
40 lines
1.8 KiB
TableGen
40 lines
1.8 KiB
TableGen
//===-- Nios2Schedule.td - Nios2 Scheduling Definitions ----*- tablegen -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Functional units across Nios2 chips sets. Based on GCC/Nios2 backend files.
|
|
//===----------------------------------------------------------------------===//
|
|
def ALU : FuncUnit;
|
|
def IMULDIV : FuncUnit;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Instruction Itinerary classes used for Nios2
|
|
//===----------------------------------------------------------------------===//
|
|
def IIAlu : InstrItinClass;
|
|
def IILoad : InstrItinClass;
|
|
def IIStore : InstrItinClass;
|
|
def IIFlush : InstrItinClass;
|
|
def IIIdiv : InstrItinClass;
|
|
def IIBranch : InstrItinClass;
|
|
|
|
def IIPseudo : InstrItinClass;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Nios2 Generic instruction itineraries.
|
|
//===----------------------------------------------------------------------===//
|
|
//@ http://llvm.org/docs/doxygen/html/structllvm_1_1InstrStage.html
|
|
def Nios2GenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
|
|
InstrItinData<IIAlu , [InstrStage<1, [ALU]>]>,
|
|
InstrItinData<IILoad , [InstrStage<3, [ALU]>]>,
|
|
InstrItinData<IIStore , [InstrStage<1, [ALU]>]>,
|
|
InstrItinData<IIFlush , [InstrStage<1, [ALU]>]>,
|
|
InstrItinData<IIIdiv , [InstrStage<38, [IMULDIV]>]>,
|
|
InstrItinData<IIBranch , [InstrStage<1, [ALU]>]>
|
|
]>;
|