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7dcf1654f8
Based ontop of D104598, which is a NFCI-ish refactoring. Here, a restriction, that only empty blocks can be merged, is lifted. Reviewed By: rnk Differential Revision: https://reviews.llvm.org/D104597
117 lines
3.6 KiB
LLVM
117 lines
3.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S | FileCheck %s
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define void @test(i32* %P, i32* %Q, i1 %A, i1 %B) {
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; CHECK-LABEL: @test(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[A_NOT:%.*]] = xor i1 [[A:%.*]], true
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; CHECK-NEXT: [[BRMERGE:%.*]] = select i1 [[A_NOT]], i1 true, i1 [[B:%.*]]
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; CHECK-NEXT: br i1 [[BRMERGE]], label [[B:%.*]], label [[COMMON_RET:%.*]]
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; CHECK: common.ret:
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; CHECK-NEXT: ret void
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; CHECK: b:
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; CHECK-NEXT: store i32 123, i32* [[P:%.*]], align 4
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; CHECK-NEXT: br label [[COMMON_RET]]
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;
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entry:
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br i1 %A, label %a, label %b
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a:
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br i1 %B, label %b, label %c
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b:
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store i32 123, i32* %P
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ret void
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c:
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ret void
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}
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; rdar://10554090
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define zeroext i1 @test2(i64 %i0, i64 %i1) nounwind uwtable readonly ssp {
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; CHECK-LABEL: @test2(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[AND_I_I:%.*]] = and i64 [[I0:%.*]], 281474976710655
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; CHECK-NEXT: [[AND_I11_I:%.*]] = and i64 [[I1:%.*]], 281474976710655
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; CHECK-NEXT: [[OR_COND:%.*]] = icmp eq i64 [[AND_I_I]], [[AND_I11_I]]
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; CHECK-NEXT: br i1 [[OR_COND]], label [[C:%.*]], label [[A:%.*]]
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; CHECK: a:
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; CHECK-NEXT: [[SHR_I4_I:%.*]] = lshr i64 [[I0]], 48
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; CHECK-NEXT: [[AND_I5_I:%.*]] = and i64 [[SHR_I4_I]], 32767
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; CHECK-NEXT: [[SHR_I_I:%.*]] = lshr i64 [[I1]], 48
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; CHECK-NEXT: [[AND_I2_I:%.*]] = and i64 [[SHR_I_I]], 32767
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; CHECK-NEXT: [[CMP9_I:%.*]] = icmp ult i64 [[AND_I5_I]], [[AND_I2_I]]
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; CHECK-NEXT: br i1 [[CMP9_I]], label [[C]], label [[B:%.*]]
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; CHECK: b:
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; CHECK-NEXT: [[SHR_I13_I9:%.*]] = lshr i64 [[I1]], 48
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; CHECK-NEXT: [[AND_I14_I10:%.*]] = and i64 [[SHR_I13_I9]], 32767
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; CHECK-NEXT: [[SHR_I_I11:%.*]] = lshr i64 [[I0]], 48
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; CHECK-NEXT: [[AND_I11_I12:%.*]] = and i64 [[SHR_I_I11]], 32767
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; CHECK-NEXT: [[PHITMP:%.*]] = icmp uge i64 [[AND_I14_I10]], [[AND_I11_I12]]
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; CHECK-NEXT: br label [[C]]
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; CHECK: c:
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; CHECK-NEXT: [[O2:%.*]] = phi i1 [ false, [[A]] ], [ [[PHITMP]], [[B]] ], [ false, [[ENTRY:%.*]] ]
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; CHECK-NEXT: ret i1 [[O2]]
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;
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entry:
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%and.i.i = and i64 %i0, 281474976710655
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%and.i11.i = and i64 %i1, 281474976710655
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%or.cond = icmp eq i64 %and.i.i, %and.i11.i
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br i1 %or.cond, label %c, label %a
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a:
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%shr.i4.i = lshr i64 %i0, 48
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%and.i5.i = and i64 %shr.i4.i, 32767
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%shr.i.i = lshr i64 %i1, 48
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%and.i2.i = and i64 %shr.i.i, 32767
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%cmp9.i = icmp ult i64 %and.i5.i, %and.i2.i
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br i1 %cmp9.i, label %c, label %b
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b:
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%shr.i13.i9 = lshr i64 %i1, 48
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%and.i14.i10 = and i64 %shr.i13.i9, 32767
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%shr.i.i11 = lshr i64 %i0, 48
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%and.i11.i12 = and i64 %shr.i.i11, 32767
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%phitmp = icmp uge i64 %and.i14.i10, %and.i11.i12
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br label %c
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c:
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%o2 = phi i1 [ false, %a ], [ %phitmp, %b ], [ false, %entry ]
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ret i1 %o2
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}
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; PR13180
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define void @pr13180(i8 %p) {
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; CHECK-LABEL: @pr13180(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: unreachable
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;
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entry:
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%tobool = icmp eq i8 %p, 0
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br i1 %tobool, label %cond.false, label %cond.true
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cond.true: ; preds = %entry
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br label %cond.end
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cond.false: ; preds = %entry
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%phitmp = icmp eq i8 %p, 0
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br label %cond.end
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cond.end: ; preds = %cond.false, %cond.true
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%cond = phi i1 [ undef, %cond.true ], [ %phitmp, %cond.false ]
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unreachable
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}
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declare void @foo()
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define void @test3() {
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; CHECK-LABEL: @test3(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: call void @foo()
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; CHECK-NEXT: ret void
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;
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entry:
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br i1 0, label %bb0, label %bb0
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bb0:
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call void @foo()
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ret void
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}
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