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4ca961430f
The new target machines are: nvptx (old ptx32) => 32-bit PTX nvptx64 (old ptx64) => 64-bit PTX The sources are based on the internal NVIDIA NVPTX back-end, and contain more functionality than the current PTX back-end currently provides. NV_CONTRIB llvm-svn: 156196
56 lines
1.7 KiB
LLVM
56 lines
1.7 KiB
LLVM
; RUN: llc < %s -march=nvptx -mcpu=sm_10 | FileCheck %s
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; RUN: llc < %s -march=nvptx64 -mcpu=sm_10 | FileCheck %s
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; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
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; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s
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@texture = internal addrspace(1) global i64 0, align 8
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; CHECK: .global .texref texture
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@surface = internal addrspace(1) global i64 0, align 8
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; CHECK: .global .surfref surface
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; CHECK: .entry kernel_func_maxntid
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define void @kernel_func_maxntid(float* %a) {
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; CHECK: .maxntid 10, 20, 30
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; CHECK: ret
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ret void
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}
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; CHECK: .entry kernel_func_reqntid
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define void @kernel_func_reqntid(float* %a) {
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; CHECK: .reqntid 11, 22, 33
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; CHECK: ret
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ret void
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}
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; CHECK: .entry kernel_func_minctasm
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define void @kernel_func_minctasm(float* %a) {
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; CHECK: .minnctapersm 42
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; CHECK: ret
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ret void
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}
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!nvvm.annotations = !{!1, !2, !3, !4, !5, !6, !7, !8}
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!1 = metadata !{void (float*)* @kernel_func_maxntid, metadata !"kernel", i32 1}
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!2 = metadata !{void (float*)* @kernel_func_maxntid,
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metadata !"maxntidx", i32 10,
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metadata !"maxntidy", i32 20,
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metadata !"maxntidz", i32 30}
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!3 = metadata !{void (float*)* @kernel_func_reqntid, metadata !"kernel", i32 1}
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!4 = metadata !{void (float*)* @kernel_func_reqntid,
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metadata !"reqntidx", i32 11,
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metadata !"reqntidy", i32 22,
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metadata !"reqntidz", i32 33}
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!5 = metadata !{void (float*)* @kernel_func_minctasm, metadata !"kernel", i32 1}
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!6 = metadata !{void (float*)* @kernel_func_minctasm,
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metadata !"minctasm", i32 42}
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!7 = metadata !{i64 addrspace(1)* @texture, metadata !"texture", i32 1}
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!8 = metadata !{i64 addrspace(1)* @surface, metadata !"surface", i32 1}
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