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225 lines
7.6 KiB
C++
225 lines
7.6 KiB
C++
//===-- SparcV9RegClassInfo.h - Register class def'ns for SparcV9 -*- C++ -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the register classes used by the SparcV9 target. It
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// implicitly defines (using enums) the "class register numbers" used in
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// the SparcV9 target, which are converted using a formula in the SparcV9RegInfo
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// class to "unified register numbers".
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//
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//===----------------------------------------------------------------------===//
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#ifndef SPARCV9REGCLASSINFO_H
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#define SPARCV9REGCLASSINFO_H
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#include "SparcV9RegInfo.h"
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namespace llvm {
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//-----------------------------------------------------------------------------
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// Integer Register Class
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//-----------------------------------------------------------------------------
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struct SparcV9IntRegClass : public TargetRegClassInfo {
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SparcV9IntRegClass(unsigned ID)
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: TargetRegClassInfo(ID, NumOfAvailRegs, NumOfAllRegs) { }
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void colorIGNode(IGNode *Node,
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const std::vector<bool> &IsColorUsedArr) const;
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inline bool isRegVolatile(int Reg) const {
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return (Reg < (int)StartOfNonVolatileRegs);
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}
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inline bool modifiedByCall(int Reg) const {
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return Reg==(int)ModifiedByCall;
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}
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enum { // colors possible for a LR (in preferred order)
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// --- following colors are volatile across function calls
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// %g0 can't be used for coloring - always 0
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o0, o1, o2, o3, o4, o5, o7, // %o0-%o5,
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// %o6 is sp,
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// all %0's can get modified by a call
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// --- following colors are NON-volatile across function calls
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l0, l1, l2, l3, l4, l5, l6, l7, // %l0-%l7
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i0, i1, i2, i3, i4, i5, // %i0-%i5: i's need not be preserved
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// %i6 is the fp - so not allocated
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// %i7 is the ret address by convention - can be used for others
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// max # of colors reg coloring can allocate (NumOfAvailRegs)
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// --- following colors are not available for allocation within this phase
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// --- but can appear for pre-colored ranges
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i6, i7, g0, g1, g2, g3, g4, g5, g6, g7, o6,
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NumOfAllRegs, // Must be first AFTER registers...
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//*** NOTE: If we decide to use some %g regs, they are volatile
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// (see sparc64ABI)
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// Move the %g regs from the end of the enumeration to just above the
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// enumeration of %o0 (change StartOfAllRegs below)
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// change isRegVloatile method below
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// Also change IntRegNames above.
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// max # of colors reg coloring can allocate
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NumOfAvailRegs = i6,
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StartOfNonVolatileRegs = l0,
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StartOfAllRegs = o0,
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ModifiedByCall = o7,
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};
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const char * const getRegName(unsigned reg) const;
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};
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//-----------------------------------------------------------------------------
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// Float Register Class
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//-----------------------------------------------------------------------------
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class SparcV9FloatRegClass : public TargetRegClassInfo {
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int findFloatColor(const LiveRange *LR, unsigned Start,
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unsigned End,
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const std::vector<bool> &IsColorUsedArr) const;
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public:
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SparcV9FloatRegClass(unsigned ID)
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: TargetRegClassInfo(ID, NumOfAvailRegs, NumOfAllRegs) {}
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// This method marks the registers used for a given register number.
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// This marks a single register for Float regs, but the R,R+1 pair
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// for double-precision registers.
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//
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virtual void markColorsUsed(unsigned RegInClass,
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int UserRegType,
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int RegTypeWanted,
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std::vector<bool> &IsColorUsedArr) const;
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// This method finds unused registers of the specified register type,
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// using the given "used" flag array IsColorUsedArr. It checks a single
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// entry in the array directly for float regs, and checks the pair [R,R+1]
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// for double-precision registers
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// It returns -1 if no unused color is found.
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//
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virtual int findUnusedColor(int RegTypeWanted,
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const std::vector<bool> &IsColorUsedArr) const;
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void colorIGNode(IGNode *Node,
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const std::vector<bool> &IsColorUsedArr) const;
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// according to SparcV9 64 ABI, all %fp regs are volatile
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inline bool isRegVolatile(int Reg) const { return true; }
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enum {
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f0, f1, f2, f3, f4, f5, f6, f7, f8, f9,
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f10, f11, f12, f13, f14, f15, f16, f17, f18, f19,
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f20, f21, f22, f23, f24, f25, f26, f27, f28, f29,
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f30, f31, f32, f33, f34, f35, f36, f37, f38, f39,
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f40, f41, f42, f43, f44, f45, f46, f47, f48, f49,
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f50, f51, f52, f53, f54, f55, f56, f57, f58, f59,
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f60, f61, f62, f63,
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// there are 64 regs alltogether but only 32 regs can be allocated at
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// a time.
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//
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NumOfAvailRegs = 32,
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NumOfAllRegs = 64,
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StartOfNonVolatileRegs = f32,
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StartOfAllRegs = f0,
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};
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const char * const getRegName(unsigned reg) const;
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};
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//-----------------------------------------------------------------------------
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// Int CC Register Class
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// Only one integer cc register is available. However, this register is
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// referred to as %xcc or %icc when instructions like subcc are executed but
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// referred to as %ccr (i.e., %xcc . %icc") when this register is moved
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// into an integer register using RD or WR instrcutions. So, three ids are
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// allocated for the three names.
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//-----------------------------------------------------------------------------
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struct SparcV9IntCCRegClass : public TargetRegClassInfo {
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SparcV9IntCCRegClass(unsigned ID)
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: TargetRegClassInfo(ID, 1, 3) { }
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void colorIGNode(IGNode *Node,
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const std::vector<bool> &IsColorUsedArr) const;
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// according to the 64-bit SparcV9 ABI, all integer CC regs are
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// volatile.
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inline bool isRegVolatile(int Reg) const { return true; }
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enum {
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xcc, icc, ccr // only one is available - see the note above
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};
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const char * const getRegName(unsigned reg) const;
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};
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//-----------------------------------------------------------------------------
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// Float CC Register Class
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// Only 4 Float CC registers are available for allocation.
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//-----------------------------------------------------------------------------
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struct SparcV9FloatCCRegClass : public TargetRegClassInfo {
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SparcV9FloatCCRegClass(unsigned ID)
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: TargetRegClassInfo(ID, 4, 4) { }
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void colorIGNode(IGNode *Node,
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const std::vector<bool> &IsColorUsedArr) const;
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// according to the 64-bit SparcV9 ABI, all floating-point CC regs are
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// volatile.
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inline bool isRegVolatile(int Reg) const { return true; }
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enum {
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fcc0, fcc1, fcc2, fcc3
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};
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const char * const getRegName(unsigned reg) const;
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};
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//-----------------------------------------------------------------------------
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// SparcV9 special register class. These registers are not used for allocation
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// but are used as arguments of some instructions.
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//-----------------------------------------------------------------------------
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struct SparcV9SpecialRegClass : public TargetRegClassInfo {
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SparcV9SpecialRegClass(unsigned ID)
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: TargetRegClassInfo(ID, 0, 1) { }
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void colorIGNode(IGNode *Node,
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const std::vector<bool> &IsColorUsedArr) const {
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assert(0 && "SparcV9SpecialRegClass should never be used for allocation");
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}
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// all currently included special regs are volatile
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inline bool isRegVolatile(int Reg) const { return true; }
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enum {
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fsr // floating point state register
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};
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const char * const getRegName(unsigned reg) const;
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};
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} // End llvm namespace
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#endif
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