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f3b7304d30
This is recommit of 4c8fb7ddd6fa49258e0e9427e7345fb56ba522d4. MIR in one unit test had mismatched types. For vectors we consider a bit as known if it is the same for all demanded vector elements (all elements by default). KnownBits BitWidth for vector type is size of vector element. Add support for G_BUILD_VECTOR. This allows combines of urem_pow2_to_mask in pre-legalizer combiner. Differential Revision: https://reviews.llvm.org/D96122 |
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.. | ||
GlobalISel | ||
AArch64SelectionDAGTest.cpp | ||
AllocationOrderTest.cpp | ||
AsmPrinterDwarfTest.cpp | ||
CMakeLists.txt | ||
DIEHashTest.cpp | ||
DIETest.cpp | ||
LexicalScopesTest.cpp | ||
LowLevelTypeTest.cpp | ||
MachineInstrBundleIteratorTest.cpp | ||
MachineInstrTest.cpp | ||
MachineOperandTest.cpp | ||
MFCommon.inc | ||
PassManagerTest.cpp | ||
ScalableVectorMVTsTest.cpp | ||
SelectionDAGAddressAnalysisTest.cpp | ||
TargetOptionsTest.cpp | ||
TestAsmPrinter.cpp | ||
TestAsmPrinter.h | ||
TypeTraitsTest.cpp |