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c0e9308c17
Refactor the scheduling predicates based on `MCInstPredicate`. In this case, `AArch64InstrInfo::hasExtendedReg()`. Differential revision: https://reviews.llvm.org/D54822 llvm-svn: 347599
109 lines
5.4 KiB
TableGen
109 lines
5.4 KiB
TableGen
//===- AArch64SchedPredicates.td - AArch64 Sched Preds -----*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines scheduling predicate definitions that are used by the
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// AArch64 subtargets.
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//
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//===----------------------------------------------------------------------===//
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// Function mappers.
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// Check the extension type in the register offset addressing mode.
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let FunctionMapper = "AArch64_AM::getMemExtendType" in {
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def CheckMemExtUXTW : CheckImmOperand_s<3, "AArch64_AM::UXTW">;
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def CheckMemExtLSL : CheckImmOperand_s<3, "AArch64_AM::UXTX">;
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def CheckMemExtSXTW : CheckImmOperand_s<3, "AArch64_AM::SXTW">;
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def CheckMemExtSXTX : CheckImmOperand_s<3, "AArch64_AM::SXTX">;
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}
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// Check for scaling in the register offset addressing mode.
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let FunctionMapper = "AArch64_AM::getMemDoShift" in
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def CheckMemScaled : CheckImmOperandSimple<3>;
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// Generic predicates.
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// Identify arithmetic instructions with extend.
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def IsArithExtPred : CheckOpcode<[ADDWrx, ADDXrx, ADDXrx64, ADDSWrx, ADDSXrx, ADDSXrx64,
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SUBWrx, SUBXrx, SUBXrx64, SUBSWrx, SUBSXrx, SUBSXrx64]>;
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// Identify arithmetic instructions with shift.
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def IsArithShiftPred : CheckOpcode<[ADDWrs, ADDXrs, ADDSWrs, ADDSXrs,
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SUBWrs, SUBXrs, SUBSWrs, SUBSXrs]>;
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// Identify logic instructions with shift.
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def IsLogicShiftPred : CheckOpcode<[ANDWrs, ANDXrs, ANDSWrs, ANDSXrs,
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BICWrs, BICXrs, BICSWrs, BICSXrs,
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EONWrs, EONXrs,
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EORWrs, EORXrs,
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ORNWrs, ORNXrs,
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ORRWrs, ORRXrs]>;
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// Identify arithmetic and logic instructions with shift.
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def IsArithLogicShiftPred : CheckAny<[IsArithShiftPred, IsLogicShiftPred]>;
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// Identify whether an instruction is a load
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// using the register offset addressing mode.
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def IsLoadRegOffsetPred : CheckOpcode<[PRFMroW, PRFMroX,
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LDRBBroW, LDRBBroX,
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LDRSBWroW, LDRSBWroX, LDRSBXroW, LDRSBXroX,
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LDRHHroW, LDRHHroX,
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LDRSHWroW, LDRSHWroX, LDRSHXroW, LDRSHXroX,
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LDRWroW, LDRWroX,
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LDRSWroW, LDRSWroX,
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LDRXroW, LDRXroX,
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LDRBroW, LDRBroX,
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LDRHroW, LDRHroX,
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LDRSroW, LDRSroX,
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LDRDroW, LDRDroX]>;
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// Identify whether an instruction is a load
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// using the register offset addressing mode.
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def IsStoreRegOffsetPred : CheckOpcode<[STRBBroW, STRBBroX,
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STRHHroW, STRHHroX,
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STRWroW, STRWroX,
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STRXroW, STRXroX,
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STRBroW, STRBroX,
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STRHroW, STRHroX,
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STRSroW, STRSroX,
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STRDroW, STRDroX]>;
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// Target predicates.
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// Identify arithmetic instructions with an extended register.
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def RegExtendedFn : TIIPredicate<"hasExtendedReg",
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MCOpcodeSwitchStatement<
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[MCOpcodeSwitchCase<
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IsArithExtPred.ValidOpcodes,
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MCReturnStatement<CheckNot<CheckZeroOperand<3>>>>],
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MCReturnStatement<FalsePred>>>;
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def RegExtendedPred : MCSchedPredicate<RegExtendedFn>;
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// Identify arithmetic and logic instructions with a shifted register.
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def RegShiftedFn : TIIPredicate<"hasShiftedReg",
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MCOpcodeSwitchStatement<
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[MCOpcodeSwitchCase<
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!listconcat(IsArithShiftPred.ValidOpcodes,
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IsLogicShiftPred.ValidOpcodes),
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MCReturnStatement<CheckNot<CheckZeroOperand<3>>>>],
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MCReturnStatement<FalsePred>>>;
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def RegShiftedPred : MCSchedPredicate<RegShiftedFn>;
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// Identify a load or store using the register offset addressing mode
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// with an extended or scaled register.
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def ScaledIdxFn : TIIPredicate<"isScaledAddr",
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MCOpcodeSwitchStatement<
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[MCOpcodeSwitchCase<
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!listconcat(IsLoadRegOffsetPred.ValidOpcodes,
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IsStoreRegOffsetPred.ValidOpcodes),
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MCReturnStatement<
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CheckAny<[CheckNot<CheckMemExtLSL>,
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CheckMemScaled]>>>],
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MCReturnStatement<FalsePred>>>;
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def ScaledIdxPred : MCSchedPredicate<ScaledIdxFn>;
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