mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-25 12:12:47 +01:00
536cf1b13f
- Rename runOnMethod to runOnFunction
* Transform getAnalysisUsageInfo into getAnalysisUsage
- Method is now const
- It now takes one AnalysisUsage object to fill in instead of 3 vectors
to fill in
- Pass's now specify which other passes they _preserve_ not which ones
they modify (be conservative!)
- A pass can specify that it preserves all analyses (because it never
modifies the underlying program)
* s/Method/Function/g in other random places as well
llvm-svn: 2333
40 lines
1.4 KiB
C++
40 lines
1.4 KiB
C++
//===-- InstrScheduling.h - Interface To Instruction Scheduling --*- C++ -*-==//
|
|
//
|
|
// This file defines a minimal, but complete, interface to instruction
|
|
// scheduling.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#ifndef LLVM_CODEGEN_INSTR_SCHEDULING_H
|
|
#define LLVM_CODEGEN_INSTR_SCHEDULING_H
|
|
|
|
class Pass;
|
|
class TargetMachine;
|
|
|
|
//---------------------------------------------------------------------------
|
|
// Function: createScheduleInstructionsWithSSAPass(..)
|
|
//
|
|
// Purpose:
|
|
// Entry point for instruction scheduling on SSA form.
|
|
// Schedules the machine instructions generated by instruction selection.
|
|
// Assumes that register allocation has not been done, i.e., operands
|
|
// are still in SSA form.
|
|
//---------------------------------------------------------------------------
|
|
|
|
Pass *createInstructionSchedulingWithSSAPass(const TargetMachine &Target);
|
|
|
|
|
|
//---------------------------------------------------------------------------
|
|
// Function: ScheduleInstructions
|
|
//
|
|
// Purpose:
|
|
// Entry point for instruction scheduling on machine code.
|
|
// Schedules the machine instructions generated by instruction selection.
|
|
// Assumes that register allocation has been done.
|
|
//---------------------------------------------------------------------------
|
|
|
|
// Not implemented yet.
|
|
//bool ScheduleInstructions(Method *M, const TargetMachine &Target);
|
|
|
|
#endif
|