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https://github.com/RPCS3/llvm-mirror.git
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eb996ef33b
Summary: This change extends MachineCopyPropagation to do COPY source forwarding and adds an additional run of the pass to the default pass pipeline just after register allocation. This version of this patch uses the newly added MachineOperand::isRenamable bit to avoid forwarding registers is such a way as to violate constraints that aren't captured in the Machine IR (e.g. ABI or ISA constraints). This change is a continuation of the work started in D30751. Reviewers: qcolombet, javed.absar, MatzeB, jonpa, tstellar Subscribers: tpr, mgorny, mcrosier, nhaehnle, nemanjai, jyknight, hfinkel, arsenm, inouehrs, eraman, sdardis, guyblank, fedor.sergeev, aheejin, dschuff, jfb, myatsina, llvm-commits Differential Revision: https://reviews.llvm.org/D41835 llvm-svn: 323991
270 lines
9.6 KiB
LLVM
270 lines
9.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; Tests for SSE1 and below, without SSE2+.
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; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=pentium3 -O3 | FileCheck %s --check-prefix=X32
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-sse2,+sse -O3 | FileCheck %s --check-prefix=X64
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; PR7993
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;define <4 x i32> @test3(<4 x i16> %a) nounwind {
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; %c = sext <4 x i16> %a to <4 x i32> ; <<4 x i32>> [#uses=1]
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; ret <4 x i32> %c
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;}
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; This should not emit shuffles to populate the top 2 elements of the 4-element
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; vector that this ends up returning.
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; rdar://8368414
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define <2 x float> @test4(<2 x float> %A, <2 x float> %B) nounwind {
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; X32-LABEL: test4:
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; X32: # %bb.0: # %entry
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; X32-NEXT: movaps %xmm0, %xmm2
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; X32-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm0[2,3]
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; X32-NEXT: addss %xmm1, %xmm0
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; X32-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,2,3]
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; X32-NEXT: subss %xmm1, %xmm2
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; X32-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
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; X32-NEXT: retl
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;
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; X64-LABEL: test4:
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; X64: # %bb.0: # %entry
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; X64-NEXT: movaps %xmm0, %xmm2
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; X64-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm0[2,3]
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; X64-NEXT: addss %xmm1, %xmm0
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; X64-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,2,3]
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; X64-NEXT: subss %xmm1, %xmm2
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; X64-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
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; X64-NEXT: retq
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entry:
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%tmp7 = extractelement <2 x float> %A, i32 0
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%tmp5 = extractelement <2 x float> %A, i32 1
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%tmp3 = extractelement <2 x float> %B, i32 0
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%tmp1 = extractelement <2 x float> %B, i32 1
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%add.r = fadd float %tmp7, %tmp3
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%add.i = fsub float %tmp5, %tmp1
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%tmp11 = insertelement <2 x float> undef, float %add.r, i32 0
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%tmp9 = insertelement <2 x float> %tmp11, float %add.i, i32 1
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ret <2 x float> %tmp9
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}
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; We used to get stuck in type legalization for this example when lowering the
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; vselect. With SSE1 v4f32 is a legal type but v4i1 (or any vector integer type)
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; is not. We used to ping pong between splitting the vselect for the v4i
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; condition operand and widening the resulting vselect for the v4f32 result.
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; PR18036
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define <4 x float> @vselect(<4 x float>*%p, <4 x i32> %q) {
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; X32-LABEL: vselect:
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; X32: # %bb.0: # %entry
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; X32-NEXT: cmpl $0, {{[0-9]+}}(%esp)
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; X32-NEXT: xorps %xmm0, %xmm0
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; X32-NEXT: je .LBB1_1
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; X32-NEXT: # %bb.2: # %entry
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; X32-NEXT: xorps %xmm1, %xmm1
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; X32-NEXT: cmpl $0, {{[0-9]+}}(%esp)
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; X32-NEXT: jne .LBB1_5
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; X32-NEXT: .LBB1_4:
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; X32-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
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; X32-NEXT: cmpl $0, {{[0-9]+}}(%esp)
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; X32-NEXT: jne .LBB1_8
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; X32-NEXT: .LBB1_7:
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; X32-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
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; X32-NEXT: cmpl $0, {{[0-9]+}}(%esp)
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; X32-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
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; X32-NEXT: je .LBB1_10
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; X32-NEXT: jmp .LBB1_11
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; X32-NEXT: .LBB1_1:
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; X32-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; X32-NEXT: cmpl $0, {{[0-9]+}}(%esp)
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; X32-NEXT: je .LBB1_4
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; X32-NEXT: .LBB1_5: # %entry
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; X32-NEXT: xorps %xmm2, %xmm2
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; X32-NEXT: cmpl $0, {{[0-9]+}}(%esp)
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; X32-NEXT: je .LBB1_7
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; X32-NEXT: .LBB1_8: # %entry
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; X32-NEXT: xorps %xmm3, %xmm3
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; X32-NEXT: cmpl $0, {{[0-9]+}}(%esp)
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; X32-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
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; X32-NEXT: jne .LBB1_11
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; X32-NEXT: .LBB1_10:
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; X32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X32-NEXT: .LBB1_11: # %entry
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; X32-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
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; X32-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]
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; X32-NEXT: retl
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;
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; X64-LABEL: vselect:
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; X64: # %bb.0: # %entry
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; X64-NEXT: testl %edx, %edx
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; X64-NEXT: xorps %xmm0, %xmm0
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; X64-NEXT: je .LBB1_1
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; X64-NEXT: # %bb.2: # %entry
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; X64-NEXT: xorps %xmm1, %xmm1
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; X64-NEXT: testl %ecx, %ecx
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; X64-NEXT: jne .LBB1_5
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; X64-NEXT: .LBB1_4:
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; X64-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
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; X64-NEXT: testl %r8d, %r8d
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; X64-NEXT: jne .LBB1_8
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; X64-NEXT: .LBB1_7:
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; X64-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
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; X64-NEXT: testl %esi, %esi
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; X64-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
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; X64-NEXT: je .LBB1_10
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; X64-NEXT: jmp .LBB1_11
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; X64-NEXT: .LBB1_1:
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; X64-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; X64-NEXT: testl %ecx, %ecx
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; X64-NEXT: je .LBB1_4
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; X64-NEXT: .LBB1_5: # %entry
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; X64-NEXT: xorps %xmm2, %xmm2
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; X64-NEXT: testl %r8d, %r8d
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; X64-NEXT: je .LBB1_7
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; X64-NEXT: .LBB1_8: # %entry
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; X64-NEXT: xorps %xmm3, %xmm3
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; X64-NEXT: testl %esi, %esi
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; X64-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
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; X64-NEXT: jne .LBB1_11
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; X64-NEXT: .LBB1_10:
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; X64-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X64-NEXT: .LBB1_11: # %entry
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; X64-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
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; X64-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]
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; X64-NEXT: retq
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entry:
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%a1 = icmp eq <4 x i32> %q, zeroinitializer
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%a14 = select <4 x i1> %a1, <4 x float> <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+0> , <4 x float> zeroinitializer
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ret <4 x float> %a14
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}
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; v4i32 isn't legal for SSE1, but this should be cmpps.
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define <4 x float> @PR28044(<4 x float> %a0, <4 x float> %a1) nounwind {
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; X32-LABEL: PR28044:
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; X32: # %bb.0:
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; X32-NEXT: cmpeqps %xmm1, %xmm0
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; X32-NEXT: retl
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;
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; X64-LABEL: PR28044:
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; X64: # %bb.0:
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; X64-NEXT: cmpeqps %xmm1, %xmm0
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; X64-NEXT: retq
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%cmp = fcmp oeq <4 x float> %a0, %a1
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%sext = sext <4 x i1> %cmp to <4 x i32>
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%res = bitcast <4 x i32> %sext to <4 x float>
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ret <4 x float> %res
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}
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; Don't crash trying to do the impossible: an integer vector comparison doesn't exist, so we must scalarize.
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; https://llvm.org/bugs/show_bug.cgi?id=30512
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define <4 x i32> @PR30512(<4 x i32> %x, <4 x i32> %y) nounwind {
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; X32-LABEL: PR30512:
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; X32: # %bb.0:
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; X32-NEXT: pushl %ebx
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; X32-NEXT: pushl %edi
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; X32-NEXT: pushl %esi
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; X32-NEXT: subl $16, %esp
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X32-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X32-NEXT: movl {{[0-9]+}}(%esp), %edi
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; X32-NEXT: xorl %ebx, %ebx
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; X32-NEXT: cmpl {{[0-9]+}}(%esp), %edi
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; X32-NEXT: sete %bl
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; X32-NEXT: negl %ebx
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; X32-NEXT: movl %ebx, {{[0-9]+}}(%esp)
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; X32-NEXT: xorl %ebx, %ebx
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; X32-NEXT: cmpl {{[0-9]+}}(%esp), %esi
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; X32-NEXT: sete %bl
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; X32-NEXT: negl %ebx
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; X32-NEXT: movl %ebx, {{[0-9]+}}(%esp)
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; X32-NEXT: xorl %ebx, %ebx
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; X32-NEXT: cmpl {{[0-9]+}}(%esp), %edx
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; X32-NEXT: sete %bl
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; X32-NEXT: negl %ebx
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; X32-NEXT: movl %ebx, {{[0-9]+}}(%esp)
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; X32-NEXT: xorl %edx, %edx
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; X32-NEXT: cmpl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: sete %dl
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; X32-NEXT: negl %edx
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; X32-NEXT: movl %edx, (%esp)
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; X32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X32-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; X32-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
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; X32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X32-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
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; X32-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
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; X32-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm1[0]
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; X32-NEXT: andps {{\.LCPI.*}}, %xmm2
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; X32-NEXT: movaps %xmm2, (%eax)
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; X32-NEXT: addl $16, %esp
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; X32-NEXT: popl %esi
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; X32-NEXT: popl %edi
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; X32-NEXT: popl %ebx
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; X32-NEXT: retl $4
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;
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; X64-LABEL: PR30512:
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; X64: # %bb.0:
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; X64-NEXT: xorl %eax, %eax
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; X64-NEXT: cmpl {{[0-9]+}}(%rsp), %r8d
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; X64-NEXT: sete %al
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; X64-NEXT: negl %eax
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; X64-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
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; X64-NEXT: xorl %eax, %eax
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; X64-NEXT: cmpl {{[0-9]+}}(%rsp), %ecx
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; X64-NEXT: sete %al
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; X64-NEXT: negl %eax
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; X64-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
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; X64-NEXT: xorl %eax, %eax
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; X64-NEXT: cmpl {{[0-9]+}}(%rsp), %edx
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; X64-NEXT: sete %al
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; X64-NEXT: negl %eax
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; X64-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
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; X64-NEXT: xorl %eax, %eax
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; X64-NEXT: cmpl %r9d, %esi
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; X64-NEXT: sete %al
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; X64-NEXT: negl %eax
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; X64-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
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; X64-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X64-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; X64-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
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; X64-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X64-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
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; X64-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
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; X64-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm1[0]
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; X64-NEXT: andps {{.*}}(%rip), %xmm2
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; X64-NEXT: movaps %xmm2, (%rdi)
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: retq
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%cmp = icmp eq <4 x i32> %x, %y
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%zext = zext <4 x i1> %cmp to <4 x i32>
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ret <4 x i32> %zext
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}
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; Fragile test warning - we need to induce the generation of a vselect
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; post-legalization to cause the crash seen in:
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; https://llvm.org/bugs/show_bug.cgi?id=31672
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; Is there a way to do that without an unsafe/fast sqrt intrinsic call?
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;
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; We now no longer try to lower sqrt using rsqrt with SSE1 only as the
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; v4i32 vselect mentioned above should never have been created. We ended up
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; scalarizing it anyway.
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define <2 x float> @PR31672() #0 {
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; X32-LABEL: PR31672:
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; X32: # %bb.0:
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; X32-NEXT: sqrtps {{\.LCPI.*}}, %xmm0
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; X32-NEXT: retl
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;
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; X64-LABEL: PR31672:
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; X64: # %bb.0:
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; X64-NEXT: sqrtps {{.*}}(%rip), %xmm0
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; X64-NEXT: retq
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%t0 = call fast <2 x float> @llvm.sqrt.v2f32(<2 x float> <float 42.0, float 3.0>)
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ret <2 x float> %t0
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}
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declare <2 x float> @llvm.sqrt.v2f32(<2 x float>) #1
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attributes #0 = { nounwind "unsafe-fp-math"="true" }
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