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30264d4391
As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
242 lines
7.0 KiB
LLVM
242 lines
7.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X32
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64
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; Verify that we correctly fold target specific packed vector shifts by
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; immediate count into a simple build_vector when the elements of the vector
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; in input to the packed shift are all constants or undef.
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define <8 x i16> @test1() {
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; X32-LABEL: test1:
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; X32: # %bb.0:
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; X32-NEXT: movaps {{.*#+}} xmm0 = [8,16,32,64,8,16,32,64]
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; X32-NEXT: retl
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;
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; X64-LABEL: test1:
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; X64: # %bb.0:
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; X64-NEXT: movaps {{.*#+}} xmm0 = [8,16,32,64,8,16,32,64]
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; X64-NEXT: retq
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%1 = tail call <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16> <i16 1, i16 2, i16 4, i16 8, i16 1, i16 2, i16 4, i16 8>, i32 3)
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ret <8 x i16> %1
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}
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define <8 x i16> @test2() {
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; X32-LABEL: test2:
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; X32: # %bb.0:
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; X32-NEXT: movaps {{.*#+}} xmm0 = [0,1,2,4,0,1,2,4]
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; X32-NEXT: retl
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;
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; X64-LABEL: test2:
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; X64: # %bb.0:
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; X64-NEXT: movaps {{.*#+}} xmm0 = [0,1,2,4,0,1,2,4]
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; X64-NEXT: retq
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%1 = tail call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> <i16 4, i16 8, i16 16, i16 32, i16 4, i16 8, i16 16, i16 32>, i32 3)
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ret <8 x i16> %1
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}
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define <8 x i16> @test3() {
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; X32-LABEL: test3:
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; X32: # %bb.0:
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; X32-NEXT: movaps {{.*#+}} xmm0 = [0,1,2,4,0,1,2,4]
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; X32-NEXT: retl
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;
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; X64-LABEL: test3:
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; X64: # %bb.0:
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; X64-NEXT: movaps {{.*#+}} xmm0 = [0,1,2,4,0,1,2,4]
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; X64-NEXT: retq
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%1 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> <i16 4, i16 8, i16 16, i16 32, i16 4, i16 8, i16 16, i16 32>, i32 3)
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ret <8 x i16> %1
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}
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define <4 x i32> @test4() {
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; X32-LABEL: test4:
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; X32: # %bb.0:
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; X32-NEXT: movaps {{.*#+}} xmm0 = [8,16,32,64]
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; X32-NEXT: retl
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;
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; X64-LABEL: test4:
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; X64: # %bb.0:
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; X64-NEXT: movaps {{.*#+}} xmm0 = [8,16,32,64]
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; X64-NEXT: retq
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%1 = tail call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> <i32 1, i32 2, i32 4, i32 8>, i32 3)
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ret <4 x i32> %1
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}
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define <4 x i32> @test5() {
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; X32-LABEL: test5:
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; X32: # %bb.0:
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; X32-NEXT: movaps {{.*#+}} xmm0 = [0,1,2,4]
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; X32-NEXT: retl
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;
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; X64-LABEL: test5:
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; X64: # %bb.0:
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; X64-NEXT: movaps {{.*#+}} xmm0 = [0,1,2,4]
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; X64-NEXT: retq
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%1 = tail call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> <i32 4, i32 8, i32 16, i32 32>, i32 3)
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ret <4 x i32> %1
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}
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define <4 x i32> @test6() {
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; X32-LABEL: test6:
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; X32: # %bb.0:
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; X32-NEXT: movaps {{.*#+}} xmm0 = [0,1,2,4]
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; X32-NEXT: retl
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;
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; X64-LABEL: test6:
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; X64: # %bb.0:
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; X64-NEXT: movaps {{.*#+}} xmm0 = [0,1,2,4]
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; X64-NEXT: retq
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%1 = tail call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> <i32 4, i32 8, i32 16, i32 32>, i32 3)
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ret <4 x i32> %1
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}
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define <2 x i64> @test7() {
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; X32-LABEL: test7:
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; X32: # %bb.0:
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; X32-NEXT: movaps {{.*#+}} xmm0 = [8,0,16,0]
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; X32-NEXT: retl
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;
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; X64-LABEL: test7:
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; X64: # %bb.0:
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; X64-NEXT: movaps {{.*#+}} xmm0 = [8,16]
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; X64-NEXT: retq
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%1 = tail call <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64> <i64 1, i64 2>, i32 3)
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ret <2 x i64> %1
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}
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define <2 x i64> @test8() {
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; X32-LABEL: test8:
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; X32: # %bb.0:
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; X32-NEXT: movaps {{.*#+}} xmm0 = [1,0,2,0]
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; X32-NEXT: retl
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;
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; X64-LABEL: test8:
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; X64: # %bb.0:
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; X64-NEXT: movaps {{.*#+}} xmm0 = [1,2]
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; X64-NEXT: retq
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%1 = tail call <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64> <i64 8, i64 16>, i32 3)
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ret <2 x i64> %1
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}
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define <8 x i16> @test9() {
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; X32-LABEL: test9:
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; X32: # %bb.0:
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; X32-NEXT: movaps {{.*#+}} xmm0 = <1,1,u,u,3,u,8,16>
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; X32-NEXT: retl
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;
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; X64-LABEL: test9:
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; X64: # %bb.0:
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; X64-NEXT: movaps {{.*#+}} xmm0 = <1,1,u,u,3,u,8,16>
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; X64-NEXT: retq
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%1 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> <i16 15, i16 8, i16 undef, i16 undef, i16 31, i16 undef, i16 64, i16 128>, i32 3)
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ret <8 x i16> %1
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}
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define <4 x i32> @test10() {
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; X32-LABEL: test10:
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; X32: # %bb.0:
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; X32-NEXT: movaps {{.*#+}} xmm0 = <u,1,u,4>
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; X32-NEXT: retl
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;
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; X64-LABEL: test10:
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; X64: # %bb.0:
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; X64-NEXT: movaps {{.*#+}} xmm0 = <u,1,u,4>
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; X64-NEXT: retq
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%1 = tail call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> <i32 undef, i32 8, i32 undef, i32 32>, i32 3)
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ret <4 x i32> %1
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}
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define <2 x i64> @test11() {
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; X32-LABEL: test11:
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; X32: # %bb.0:
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; X32-NEXT: movaps {{.*#+}} xmm0 = <u,u,3,0>
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; X32-NEXT: retl
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;
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; X64-LABEL: test11:
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; X64: # %bb.0:
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; X64-NEXT: movaps {{.*#+}} xmm0 = <u,3>
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; X64-NEXT: retq
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%1 = tail call <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64> <i64 undef, i64 31>, i32 3)
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ret <2 x i64> %1
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}
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define <8 x i16> @test12() {
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; X32-LABEL: test12:
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; X32: # %bb.0:
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; X32-NEXT: movaps {{.*#+}} xmm0 = <1,1,u,u,3,u,8,16>
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; X32-NEXT: retl
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;
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; X64-LABEL: test12:
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; X64: # %bb.0:
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; X64-NEXT: movaps {{.*#+}} xmm0 = <1,1,u,u,3,u,8,16>
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; X64-NEXT: retq
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%1 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> <i16 15, i16 8, i16 undef, i16 undef, i16 31, i16 undef, i16 64, i16 128>, i32 3)
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ret <8 x i16> %1
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}
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define <4 x i32> @test13() {
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; X32-LABEL: test13:
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; X32: # %bb.0:
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; X32-NEXT: movaps {{.*#+}} xmm0 = <u,1,u,4>
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; X32-NEXT: retl
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;
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; X64-LABEL: test13:
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; X64: # %bb.0:
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; X64-NEXT: movaps {{.*#+}} xmm0 = <u,1,u,4>
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; X64-NEXT: retq
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%1 = tail call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> <i32 undef, i32 8, i32 undef, i32 32>, i32 3)
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ret <4 x i32> %1
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}
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define <8 x i16> @test14() {
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; X32-LABEL: test14:
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; X32: # %bb.0:
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; X32-NEXT: movaps {{.*#+}} xmm0 = <1,1,u,u,3,u,8,16>
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; X32-NEXT: retl
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;
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; X64-LABEL: test14:
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; X64: # %bb.0:
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; X64-NEXT: movaps {{.*#+}} xmm0 = <1,1,u,u,3,u,8,16>
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; X64-NEXT: retq
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%1 = tail call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> <i16 15, i16 8, i16 undef, i16 undef, i16 31, i16 undef, i16 64, i16 128>, i32 3)
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ret <8 x i16> %1
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}
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define <4 x i32> @test15() {
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; X32-LABEL: test15:
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; X32: # %bb.0:
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; X32-NEXT: movaps {{.*#+}} xmm0 = <u,64,u,256>
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; X32-NEXT: retl
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;
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; X64-LABEL: test15:
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; X64: # %bb.0:
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; X64-NEXT: movaps {{.*#+}} xmm0 = <u,64,u,256>
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; X64-NEXT: retq
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%1 = tail call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> <i32 undef, i32 8, i32 undef, i32 32>, i32 3)
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ret <4 x i32> %1
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}
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define <2 x i64> @test16() {
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; X32-LABEL: test16:
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; X32: # %bb.0:
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; X32-NEXT: movaps {{.*#+}} xmm0 = <u,u,248,0>
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; X32-NEXT: retl
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;
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; X64-LABEL: test16:
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; X64: # %bb.0:
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; X64-NEXT: movaps {{.*#+}} xmm0 = <u,248>
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; X64-NEXT: retq
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%1 = tail call <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64> <i64 undef, i64 31>, i32 3)
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ret <2 x i64> %1
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}
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declare <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16>, i32)
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declare <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16>, i32)
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declare <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16>, i32)
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declare <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32>, i32)
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declare <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32>, i32)
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declare <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32>, i32)
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declare <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64>, i32)
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declare <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64>, i32)
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