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432 lines
14 KiB
C++
432 lines
14 KiB
C++
//===-- X86Subtarget.cpp - X86 Subtarget Information ----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the X86 specific subclass of TargetSubtargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "subtarget"
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#include "X86Subtarget.h"
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#include "X86InstrInfo.h"
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#include "llvm/GlobalValue.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Support/Host.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#define GET_SUBTARGETINFO_TARGET_DESC
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#define GET_SUBTARGETINFO_CTOR
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#include "X86GenSubtargetInfo.inc"
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using namespace llvm;
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#if defined(_MSC_VER)
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#include <intrin.h>
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#endif
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/// ClassifyBlockAddressReference - Classify a blockaddress reference for the
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/// current subtarget according to how we should reference it in a non-pcrel
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/// context.
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unsigned char X86Subtarget::
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ClassifyBlockAddressReference() const {
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if (isPICStyleGOT()) // 32-bit ELF targets.
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return X86II::MO_GOTOFF;
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if (isPICStyleStubPIC()) // Darwin/32 in PIC mode.
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return X86II::MO_PIC_BASE_OFFSET;
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// Direct static reference to label.
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return X86II::MO_NO_FLAG;
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}
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/// ClassifyGlobalReference - Classify a global variable reference for the
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/// current subtarget according to how we should reference it in a non-pcrel
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/// context.
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unsigned char X86Subtarget::
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ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const {
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// DLLImport only exists on windows, it is implemented as a load from a
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// DLLIMPORT stub.
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if (GV->hasDLLImportLinkage())
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return X86II::MO_DLLIMPORT;
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// Determine whether this is a reference to a definition or a declaration.
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// Materializable GVs (in JIT lazy compilation mode) do not require an extra
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// load from stub.
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bool isDecl = GV->hasAvailableExternallyLinkage();
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if (GV->isDeclaration() && !GV->isMaterializable())
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isDecl = true;
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// X86-64 in PIC mode.
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if (isPICStyleRIPRel()) {
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// Large model never uses stubs.
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if (TM.getCodeModel() == CodeModel::Large)
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return X86II::MO_NO_FLAG;
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if (isTargetDarwin()) {
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// If symbol visibility is hidden, the extra load is not needed if
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// target is x86-64 or the symbol is definitely defined in the current
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// translation unit.
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if (GV->hasDefaultVisibility() &&
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(isDecl || GV->isWeakForLinker()))
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return X86II::MO_GOTPCREL;
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} else if (!isTargetWin64()) {
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assert(isTargetELF() && "Unknown rip-relative target");
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// Extra load is needed for all externally visible.
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if (!GV->hasLocalLinkage() && GV->hasDefaultVisibility())
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return X86II::MO_GOTPCREL;
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}
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return X86II::MO_NO_FLAG;
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}
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if (isPICStyleGOT()) { // 32-bit ELF targets.
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// Extra load is needed for all externally visible.
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if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
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return X86II::MO_GOTOFF;
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return X86II::MO_GOT;
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}
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if (isPICStyleStubPIC()) { // Darwin/32 in PIC mode.
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// Determine whether we have a stub reference and/or whether the reference
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// is relative to the PIC base or not.
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// If this is a strong reference to a definition, it is definitely not
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// through a stub.
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if (!isDecl && !GV->isWeakForLinker())
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return X86II::MO_PIC_BASE_OFFSET;
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// Unless we have a symbol with hidden visibility, we have to go through a
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// normal $non_lazy_ptr stub because this symbol might be resolved late.
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if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
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return X86II::MO_DARWIN_NONLAZY_PIC_BASE;
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// If symbol visibility is hidden, we have a stub for common symbol
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// references and external declarations.
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if (isDecl || GV->hasCommonLinkage()) {
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// Hidden $non_lazy_ptr reference.
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return X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE;
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}
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// Otherwise, no stub.
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return X86II::MO_PIC_BASE_OFFSET;
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}
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if (isPICStyleStubNoDynamic()) { // Darwin/32 in -mdynamic-no-pic mode.
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// Determine whether we have a stub reference.
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// If this is a strong reference to a definition, it is definitely not
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// through a stub.
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if (!isDecl && !GV->isWeakForLinker())
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return X86II::MO_NO_FLAG;
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// Unless we have a symbol with hidden visibility, we have to go through a
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// normal $non_lazy_ptr stub because this symbol might be resolved late.
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if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
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return X86II::MO_DARWIN_NONLAZY;
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// Otherwise, no stub.
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return X86II::MO_NO_FLAG;
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}
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// Direct static reference to global.
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return X86II::MO_NO_FLAG;
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}
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/// getBZeroEntry - This function returns the name of a function which has an
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/// interface like the non-standard bzero function, if such a function exists on
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/// the current subtarget and it is considered prefereable over memset with zero
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/// passed as the second argument. Otherwise it returns null.
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const char *X86Subtarget::getBZeroEntry() const {
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// Darwin 10 has a __bzero entry point for this purpose.
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if (getTargetTriple().isMacOSX() &&
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!getTargetTriple().isMacOSXVersionLT(10, 6))
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return "__bzero";
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return 0;
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}
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/// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
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/// to immediate address.
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bool X86Subtarget::IsLegalToCallImmediateAddr(const TargetMachine &TM) const {
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if (In64BitMode)
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return false;
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return isTargetELF() || TM.getRelocationModel() == Reloc::Static;
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}
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/// getSpecialAddressLatency - For targets where it is beneficial to
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/// backschedule instructions that compute addresses, return a value
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/// indicating the number of scheduling cycles of backscheduling that
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/// should be attempted.
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unsigned X86Subtarget::getSpecialAddressLatency() const {
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// For x86 out-of-order targets, back-schedule address computations so
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// that loads and stores aren't blocked.
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// This value was chosen arbitrarily.
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return 200;
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}
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void X86Subtarget::AutoDetectSubtargetFeatures() {
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unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
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unsigned MaxLevel;
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union {
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unsigned u[3];
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char c[12];
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} text;
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if (X86_MC::GetCpuIDAndInfo(0, &MaxLevel, text.u+0, text.u+2, text.u+1) ||
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MaxLevel < 1)
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return;
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X86_MC::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
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if ((EDX >> 15) & 1) { HasCMov = true; ToggleFeature(X86::FeatureCMOV); }
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if ((EDX >> 23) & 1) { X86SSELevel = MMX; ToggleFeature(X86::FeatureMMX); }
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if ((EDX >> 25) & 1) { X86SSELevel = SSE1; ToggleFeature(X86::FeatureSSE1); }
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if ((EDX >> 26) & 1) { X86SSELevel = SSE2; ToggleFeature(X86::FeatureSSE2); }
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if (ECX & 0x1) { X86SSELevel = SSE3; ToggleFeature(X86::FeatureSSE3); }
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if ((ECX >> 9) & 1) { X86SSELevel = SSSE3; ToggleFeature(X86::FeatureSSSE3);}
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if ((ECX >> 19) & 1) { X86SSELevel = SSE41; ToggleFeature(X86::FeatureSSE41);}
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if ((ECX >> 20) & 1) { X86SSELevel = SSE42; ToggleFeature(X86::FeatureSSE42);}
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if ((ECX >> 28) & 1) { X86SSELevel = AVX; ToggleFeature(X86::FeatureAVX); }
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bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0;
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bool IsAMD = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0;
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if ((ECX >> 1) & 0x1) {
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HasPCLMUL = true;
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ToggleFeature(X86::FeaturePCLMUL);
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}
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if ((ECX >> 12) & 0x1) {
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HasFMA = true;
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ToggleFeature(X86::FeatureFMA);
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}
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if (IsIntel && ((ECX >> 22) & 0x1)) {
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HasMOVBE = true;
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ToggleFeature(X86::FeatureMOVBE);
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}
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if ((ECX >> 23) & 0x1) {
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HasPOPCNT = true;
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ToggleFeature(X86::FeaturePOPCNT);
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}
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if ((ECX >> 25) & 0x1) {
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HasAES = true;
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ToggleFeature(X86::FeatureAES);
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}
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if ((ECX >> 29) & 0x1) {
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HasF16C = true;
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ToggleFeature(X86::FeatureF16C);
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}
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if (IsIntel && ((ECX >> 30) & 0x1)) {
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HasRDRAND = true;
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ToggleFeature(X86::FeatureRDRAND);
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}
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if ((ECX >> 13) & 0x1) {
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HasCmpxchg16b = true;
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ToggleFeature(X86::FeatureCMPXCHG16B);
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}
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if (IsIntel || IsAMD) {
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// Determine if bit test memory instructions are slow.
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unsigned Family = 0;
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unsigned Model = 0;
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X86_MC::DetectFamilyModel(EAX, Family, Model);
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if (IsAMD || (Family == 6 && Model >= 13)) {
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IsBTMemSlow = true;
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ToggleFeature(X86::FeatureSlowBTMem);
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}
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// If it's Nehalem, unaligned memory access is fast.
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// FIXME: Nehalem is family 6. Also include Westmere and later processors?
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if (Family == 15 && Model == 26) {
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IsUAMemFast = true;
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ToggleFeature(X86::FeatureFastUAMem);
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}
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// Set processor type. Currently only Atom is detected.
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if (Family == 6 &&
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(Model == 28 || Model == 38 || Model == 39)) {
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X86ProcFamily = IntelAtom;
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UseLeaForSP = true;
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ToggleFeature(X86::FeatureLeaForSP);
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}
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unsigned MaxExtLevel;
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X86_MC::GetCpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
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if (MaxExtLevel >= 0x80000001) {
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X86_MC::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
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if ((EDX >> 29) & 0x1) {
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HasX86_64 = true;
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ToggleFeature(X86::Feature64Bit);
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}
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if ((ECX >> 5) & 0x1) {
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HasLZCNT = true;
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ToggleFeature(X86::FeatureLZCNT);
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}
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if (IsAMD) {
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if ((ECX >> 6) & 0x1) {
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HasSSE4A = true;
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ToggleFeature(X86::FeatureSSE4A);
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}
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if ((ECX >> 11) & 0x1) {
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HasXOP = true;
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ToggleFeature(X86::FeatureXOP);
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}
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if ((ECX >> 16) & 0x1) {
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HasFMA4 = true;
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ToggleFeature(X86::FeatureFMA4);
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}
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}
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}
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}
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if (MaxLevel >= 7) {
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if (!X86_MC::GetCpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX)) {
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if (IsIntel && (EBX & 0x1)) {
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HasFSGSBase = true;
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ToggleFeature(X86::FeatureFSGSBase);
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}
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if ((EBX >> 3) & 0x1) {
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HasBMI = true;
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ToggleFeature(X86::FeatureBMI);
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}
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if (IsIntel && ((EBX >> 5) & 0x1)) {
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X86SSELevel = AVX2;
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ToggleFeature(X86::FeatureAVX2);
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}
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if (IsIntel && ((EBX >> 8) & 0x1)) {
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HasBMI2 = true;
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ToggleFeature(X86::FeatureBMI2);
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}
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}
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}
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}
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X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU,
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const std::string &FS,
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unsigned StackAlignOverride, bool is64Bit)
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: X86GenSubtargetInfo(TT, CPU, FS)
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, X86ProcFamily(Others)
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, PICStyle(PICStyles::None)
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, X86SSELevel(NoMMXSSE)
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, X863DNowLevel(NoThreeDNow)
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, HasCMov(false)
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, HasX86_64(false)
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, HasPOPCNT(false)
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, HasSSE4A(false)
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, HasAES(false)
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, HasPCLMUL(false)
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, HasFMA(false)
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, HasFMA4(false)
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, HasXOP(false)
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, HasMOVBE(false)
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, HasRDRAND(false)
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, HasF16C(false)
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, HasFSGSBase(false)
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, HasLZCNT(false)
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, HasBMI(false)
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, HasBMI2(false)
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, IsBTMemSlow(false)
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, IsUAMemFast(false)
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, HasVectorUAMem(false)
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, HasCmpxchg16b(false)
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, UseLeaForSP(false)
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, PostRAScheduler(false)
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, stackAlignment(4)
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// FIXME: this is a known good value for Yonah. How about others?
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, MaxInlineSizeThreshold(128)
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, TargetTriple(TT)
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, In64BitMode(is64Bit) {
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// Determine default and user specified characteristics
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std::string CPUName = CPU;
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if (!FS.empty() || !CPU.empty()) {
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if (CPUName.empty()) {
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#if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
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|| defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
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CPUName = sys::getHostCPUName();
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#else
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CPUName = "generic";
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#endif
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}
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// Make sure 64-bit features are available in 64-bit mode. (But make sure
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// SSE2 can be turned off explicitly.)
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std::string FullFS = FS;
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if (In64BitMode) {
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if (!FullFS.empty())
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FullFS = "+64bit,+sse2," + FullFS;
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else
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FullFS = "+64bit,+sse2";
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}
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// If feature string is not empty, parse features string.
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ParseSubtargetFeatures(CPUName, FullFS);
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} else {
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if (CPUName.empty()) {
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#if defined (__x86_64__) || defined(__i386__)
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CPUName = sys::getHostCPUName();
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#else
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CPUName = "generic";
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#endif
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}
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// Otherwise, use CPUID to auto-detect feature set.
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AutoDetectSubtargetFeatures();
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// Make sure 64-bit features are available in 64-bit mode.
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if (In64BitMode) {
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HasX86_64 = true; ToggleFeature(X86::Feature64Bit);
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HasCMov = true; ToggleFeature(X86::FeatureCMOV);
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if (X86SSELevel < SSE2) {
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X86SSELevel = SSE2;
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ToggleFeature(X86::FeatureSSE1);
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ToggleFeature(X86::FeatureSSE2);
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}
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}
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}
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if (X86ProcFamily == IntelAtom) {
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PostRAScheduler = true;
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InstrItins = getInstrItineraryForCPU(CPUName);
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}
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// It's important to keep the MCSubtargetInfo feature bits in sync with
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// target data structure which is shared with MC code emitter, etc.
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if (In64BitMode)
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ToggleFeature(X86::Mode64Bit);
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DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel
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<< ", 3DNowLevel " << X863DNowLevel
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<< ", 64bit " << HasX86_64 << "\n");
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assert((!In64BitMode || HasX86_64) &&
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"64-bit code requested on a subtarget that doesn't support it!");
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// Stack alignment is 16 bytes on Darwin, FreeBSD, Linux and Solaris (both
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// 32 and 64 bit) and for all 64-bit targets.
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if (StackAlignOverride)
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stackAlignment = StackAlignOverride;
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else if (isTargetDarwin() || isTargetFreeBSD() || isTargetLinux() ||
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isTargetSolaris() || In64BitMode)
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stackAlignment = 16;
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}
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bool X86Subtarget::enablePostRAScheduler(
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CodeGenOpt::Level OptLevel,
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TargetSubtargetInfo::AntiDepBreakMode& Mode,
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RegClassVector& CriticalPathRCs) const {
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Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
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CriticalPathRCs.clear();
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return PostRAScheduler && OptLevel >= CodeGenOpt::Default;
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}
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