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320 lines
11 KiB
C++
320 lines
11 KiB
C++
//===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the X86 specific subclass of TargetSubtargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#ifndef X86SUBTARGET_H
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#define X86SUBTARGET_H
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#include "llvm/CallingConv.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include <string>
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#define GET_SUBTARGETINFO_HEADER
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#include "X86GenSubtargetInfo.inc"
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namespace llvm {
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class GlobalValue;
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class StringRef;
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class TargetMachine;
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/// PICStyles - The X86 backend supports a number of different styles of PIC.
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///
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namespace PICStyles {
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enum Style {
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StubPIC, // Used on i386-darwin in -fPIC mode.
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StubDynamicNoPIC, // Used on i386-darwin in -mdynamic-no-pic mode.
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GOT, // Used on many 32-bit unices in -fPIC mode.
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RIPRel, // Used on X86-64 when not in -static mode.
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None // Set when in -static mode (not PIC or DynamicNoPIC mode).
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};
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}
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class X86Subtarget : public X86GenSubtargetInfo {
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protected:
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enum X86SSEEnum {
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NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2
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};
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enum X863DNowEnum {
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NoThreeDNow, ThreeDNow, ThreeDNowA
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};
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enum X86ProcFamilyEnum {
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Others, IntelAtom
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};
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/// X86ProcFamily - X86 processor family: Intel Atom, and others
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X86ProcFamilyEnum X86ProcFamily;
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/// PICStyle - Which PIC style to use
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///
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PICStyles::Style PICStyle;
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/// X86SSELevel - MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or
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/// none supported.
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X86SSEEnum X86SSELevel;
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/// X863DNowLevel - 3DNow or 3DNow Athlon, or none supported.
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///
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X863DNowEnum X863DNowLevel;
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/// HasCMov - True if this processor has conditional move instructions
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/// (generally pentium pro+).
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bool HasCMov;
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/// HasX86_64 - True if the processor supports X86-64 instructions.
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///
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bool HasX86_64;
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/// HasPOPCNT - True if the processor supports POPCNT.
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bool HasPOPCNT;
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/// HasSSE4A - True if the processor supports SSE4A instructions.
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bool HasSSE4A;
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/// HasAES - Target has AES instructions
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bool HasAES;
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/// HasPCLMUL - Target has carry-less multiplication
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bool HasPCLMUL;
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/// HasFMA - Target has 3-operand fused multiply-add
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bool HasFMA;
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/// HasFMA4 - Target has 4-operand fused multiply-add
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bool HasFMA4;
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/// HasXOP - Target has XOP instructions
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bool HasXOP;
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/// HasMOVBE - True if the processor has the MOVBE instruction.
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bool HasMOVBE;
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/// HasRDRAND - True if the processor has the RDRAND instruction.
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bool HasRDRAND;
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/// HasF16C - Processor has 16-bit floating point conversion instructions.
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bool HasF16C;
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/// HasFSGSBase - Processor has FS/GS base insturctions.
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bool HasFSGSBase;
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/// HasLZCNT - Processor has LZCNT instruction.
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bool HasLZCNT;
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/// HasBMI - Processor has BMI1 instructions.
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bool HasBMI;
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/// HasBMI2 - Processor has BMI2 instructions.
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bool HasBMI2;
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/// IsBTMemSlow - True if BT (bit test) of memory instructions are slow.
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bool IsBTMemSlow;
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/// IsUAMemFast - True if unaligned memory access is fast.
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bool IsUAMemFast;
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/// HasVectorUAMem - True if SIMD operations can have unaligned memory
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/// operands. This may require setting a feature bit in the processor.
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bool HasVectorUAMem;
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/// HasCmpxchg16b - True if this processor has the CMPXCHG16B instruction;
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/// this is true for most x86-64 chips, but not the first AMD chips.
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bool HasCmpxchg16b;
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/// UseLeaForSP - True if the LEA instruction should be used for adjusting
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/// the stack pointer. This is an optimization for Intel Atom processors.
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bool UseLeaForSP;
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/// PostRAScheduler - True if using post-register-allocation scheduler.
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bool PostRAScheduler;
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/// stackAlignment - The minimum alignment known to hold of the stack frame on
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/// entry to the function and which must be maintained by every function.
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unsigned stackAlignment;
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/// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
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///
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unsigned MaxInlineSizeThreshold;
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/// TargetTriple - What processor and OS we're targeting.
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Triple TargetTriple;
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/// Instruction itineraries for scheduling
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InstrItineraryData InstrItins;
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private:
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/// In64BitMode - True if compiling for 64-bit, false for 32-bit.
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bool In64BitMode;
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public:
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/// This constructor initializes the data members to match that
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/// of the specified triple.
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///
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X86Subtarget(const std::string &TT, const std::string &CPU,
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const std::string &FS,
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unsigned StackAlignOverride, bool is64Bit);
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/// getStackAlignment - Returns the minimum alignment known to hold of the
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/// stack frame on entry to the function and which must be maintained by every
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/// function for this subtarget.
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unsigned getStackAlignment() const { return stackAlignment; }
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/// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
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/// that still makes it profitable to inline the call.
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unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
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/// ParseSubtargetFeatures - Parses features string setting specified
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/// subtarget options. Definition of function is auto generated by tblgen.
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void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
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/// AutoDetectSubtargetFeatures - Auto-detect CPU features using CPUID
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/// instruction.
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void AutoDetectSubtargetFeatures();
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bool is64Bit() const { return In64BitMode; }
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PICStyles::Style getPICStyle() const { return PICStyle; }
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void setPICStyle(PICStyles::Style Style) { PICStyle = Style; }
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bool hasCMov() const { return HasCMov; }
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bool hasMMX() const { return X86SSELevel >= MMX; }
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bool hasSSE1() const { return X86SSELevel >= SSE1; }
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bool hasSSE2() const { return X86SSELevel >= SSE2; }
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bool hasSSE3() const { return X86SSELevel >= SSE3; }
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bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
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bool hasSSE41() const { return X86SSELevel >= SSE41; }
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bool hasSSE42() const { return X86SSELevel >= SSE42; }
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bool hasAVX() const { return X86SSELevel >= AVX; }
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bool hasAVX2() const { return X86SSELevel >= AVX2; }
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bool hasSSE4A() const { return HasSSE4A; }
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bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
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bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
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bool hasPOPCNT() const { return HasPOPCNT; }
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bool hasAES() const { return HasAES; }
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bool hasPCLMUL() const { return HasPCLMUL; }
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bool hasFMA() const { return HasFMA; }
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bool hasFMA4() const { return HasFMA4; }
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bool hasXOP() const { return HasXOP; }
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bool hasMOVBE() const { return HasMOVBE; }
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bool hasRDRAND() const { return HasRDRAND; }
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bool hasF16C() const { return HasF16C; }
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bool hasFSGSBase() const { return HasFSGSBase; }
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bool hasLZCNT() const { return HasLZCNT; }
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bool hasBMI() const { return HasBMI; }
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bool hasBMI2() const { return HasBMI2; }
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bool isBTMemSlow() const { return IsBTMemSlow; }
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bool isUnalignedMemAccessFast() const { return IsUAMemFast; }
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bool hasVectorUAMem() const { return HasVectorUAMem; }
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bool hasCmpxchg16b() const { return HasCmpxchg16b; }
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bool useLeaForSP() const { return UseLeaForSP; }
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bool isAtom() const { return X86ProcFamily == IntelAtom; }
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const Triple &getTargetTriple() const { return TargetTriple; }
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bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
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bool isTargetFreeBSD() const {
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return TargetTriple.getOS() == Triple::FreeBSD;
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}
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bool isTargetSolaris() const {
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return TargetTriple.getOS() == Triple::Solaris;
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}
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// ELF is a reasonably sane default and the only other X86 targets we
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// support are Darwin and Windows. Just use "not those".
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bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
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bool isTargetLinux() const { return TargetTriple.getOS() == Triple::Linux; }
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bool isTargetNaCl() const {
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return TargetTriple.getOS() == Triple::NativeClient;
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}
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bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
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bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
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bool isTargetWindows() const { return TargetTriple.getOS() == Triple::Win32; }
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bool isTargetMingw() const { return TargetTriple.getOS() == Triple::MinGW32; }
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bool isTargetCygwin() const { return TargetTriple.getOS() == Triple::Cygwin; }
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bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
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bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
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bool isTargetEnvMacho() const { return TargetTriple.isEnvironmentMachO(); }
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bool isTargetWin64() const {
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// FIXME: x86_64-cygwin has not been released yet.
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return In64BitMode && TargetTriple.isOSWindows();
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}
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bool isTargetWin32() const {
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// FIXME: Cygwin is included for isTargetWin64 -- should it be included
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// here too?
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return !In64BitMode && (isTargetMingw() || isTargetWindows());
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}
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bool isPICStyleSet() const { return PICStyle != PICStyles::None; }
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bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
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bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
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bool isPICStyleStubPIC() const {
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return PICStyle == PICStyles::StubPIC;
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}
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bool isPICStyleStubNoDynamic() const {
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return PICStyle == PICStyles::StubDynamicNoPIC;
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}
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bool isPICStyleStubAny() const {
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return PICStyle == PICStyles::StubDynamicNoPIC ||
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PICStyle == PICStyles::StubPIC; }
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/// ClassifyGlobalReference - Classify a global variable reference for the
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/// current subtarget according to how we should reference it in a non-pcrel
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/// context.
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unsigned char ClassifyGlobalReference(const GlobalValue *GV,
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const TargetMachine &TM)const;
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/// ClassifyBlockAddressReference - Classify a blockaddress reference for the
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/// current subtarget according to how we should reference it in a non-pcrel
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/// context.
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unsigned char ClassifyBlockAddressReference() const;
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/// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
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/// to immediate address.
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bool IsLegalToCallImmediateAddr(const TargetMachine &TM) const;
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/// This function returns the name of a function which has an interface
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/// like the non-standard bzero function, if such a function exists on
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/// the current subtarget and it is considered prefereable over
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/// memset with zero passed as the second argument. Otherwise it
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/// returns null.
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const char *getBZeroEntry() const;
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/// getSpecialAddressLatency - For targets where it is beneficial to
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/// backschedule instructions that compute addresses, return a value
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/// indicating the number of scheduling cycles of backscheduling that
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/// should be attempted.
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unsigned getSpecialAddressLatency() const;
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/// enablePostRAScheduler - run for Atom optimization.
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bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
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TargetSubtargetInfo::AntiDepBreakMode& Mode,
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RegClassVector& CriticalPathRCs) const;
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bool postRAScheduler() const { return PostRAScheduler; }
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/// getInstrItins = Return the instruction itineraries based on the
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/// subtarget selection.
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const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
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};
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} // End llvm namespace
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#endif
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