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261 lines
8.5 KiB
C++
261 lines
8.5 KiB
C++
//===-- MipsSERegisterInfo.cpp - MIPS32/64 Register Information -== -------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the MIPS32/64 implementation of the TargetRegisterInfo
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// class.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsSERegisterInfo.h"
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#include "Mips.h"
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#include "MipsMachineFunction.h"
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#include "MipsSEInstrInfo.h"
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#include "MipsSubtarget.h"
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#include "MipsTargetMachine.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetFrameLowering.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/DebugInfo.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/Type.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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#define DEBUG_TYPE "mips-reg-info"
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MipsSERegisterInfo::MipsSERegisterInfo() : MipsRegisterInfo() {}
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bool MipsSERegisterInfo::
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requiresRegisterScavenging(const MachineFunction &MF) const {
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return true;
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}
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bool MipsSERegisterInfo::
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requiresFrameIndexScavenging(const MachineFunction &MF) const {
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return true;
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}
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const TargetRegisterClass *
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MipsSERegisterInfo::intRegClass(unsigned Size) const {
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if (Size == 4)
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return &Mips::GPR32RegClass;
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assert(Size == 8);
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return &Mips::GPR64RegClass;
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}
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/// Get the size of the offset supported by the given load/store/inline asm.
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/// The result includes the effects of any scale factors applied to the
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/// instruction immediate.
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static inline unsigned getLoadStoreOffsetSizeInBits(const unsigned Opcode,
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MachineOperand MO) {
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switch (Opcode) {
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case Mips::LD_B:
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case Mips::ST_B:
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return 10;
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case Mips::LD_H:
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case Mips::ST_H:
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return 10 + 1 /* scale factor */;
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case Mips::LD_W:
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case Mips::ST_W:
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return 10 + 2 /* scale factor */;
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case Mips::LD_D:
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case Mips::ST_D:
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return 10 + 3 /* scale factor */;
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case Mips::LL:
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case Mips::LL64:
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case Mips::LLD:
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case Mips::LLE:
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case Mips::SC:
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case Mips::SC64:
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case Mips::SCD:
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case Mips::SCE:
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return 16;
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case Mips::LLE_MM:
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case Mips::LL_MM:
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case Mips::SCE_MM:
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case Mips::SC_MM:
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return 12;
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case Mips::LL64_R6:
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case Mips::LL_R6:
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case Mips::LLD_R6:
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case Mips::SC64_R6:
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case Mips::SCD_R6:
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case Mips::SC_R6:
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case Mips::LL_MMR6:
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case Mips::SC_MMR6:
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return 9;
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case Mips::INLINEASM: {
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unsigned ConstraintID = InlineAsm::getMemoryConstraintID(MO.getImm());
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switch (ConstraintID) {
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case InlineAsm::Constraint_ZC: {
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const MipsSubtarget &Subtarget = MO.getParent()
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->getParent()
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->getParent()
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->getSubtarget<MipsSubtarget>();
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if (Subtarget.inMicroMipsMode())
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return 12;
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if (Subtarget.hasMips32r6())
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return 9;
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return 16;
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}
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default:
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return 16;
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}
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}
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default:
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return 16;
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}
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}
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/// Get the scale factor applied to the immediate in the given load/store.
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static inline unsigned getLoadStoreOffsetAlign(const unsigned Opcode) {
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switch (Opcode) {
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case Mips::LD_H:
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case Mips::ST_H:
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return 2;
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case Mips::LD_W:
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case Mips::ST_W:
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return 4;
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case Mips::LD_D:
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case Mips::ST_D:
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return 8;
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default:
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return 1;
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}
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}
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void MipsSERegisterInfo::eliminateFI(MachineBasicBlock::iterator II,
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unsigned OpNo, int FrameIndex,
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uint64_t StackSize,
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int64_t SPOffset) const {
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MachineInstr &MI = *II;
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MachineFunction &MF = *MI.getParent()->getParent();
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MachineFrameInfo &MFI = MF.getFrameInfo();
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MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
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MipsABIInfo ABI =
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static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI();
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const MipsRegisterInfo *RegInfo =
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static_cast<const MipsRegisterInfo *>(MF.getSubtarget().getRegisterInfo());
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const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
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int MinCSFI = 0;
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int MaxCSFI = -1;
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if (CSI.size()) {
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MinCSFI = CSI[0].getFrameIdx();
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MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
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}
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bool EhDataRegFI = MipsFI->isEhDataRegFI(FrameIndex);
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bool IsISRRegFI = MipsFI->isISRRegFI(FrameIndex);
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// The following stack frame objects are always referenced relative to $sp:
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// 1. Outgoing arguments.
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// 2. Pointer to dynamically allocated stack space.
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// 3. Locations for callee-saved registers.
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// 4. Locations for eh data registers.
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// 5. Locations for ISR saved Coprocessor 0 registers 12 & 14.
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// Everything else is referenced relative to whatever register
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// getFrameRegister() returns.
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unsigned FrameReg;
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if ((FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI) || EhDataRegFI ||
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IsISRRegFI)
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FrameReg = ABI.GetStackPtr();
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else if (RegInfo->needsStackRealignment(MF)) {
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if (MFI.hasVarSizedObjects() && !MFI.isFixedObjectIndex(FrameIndex))
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FrameReg = ABI.GetBasePtr();
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else if (MFI.isFixedObjectIndex(FrameIndex))
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FrameReg = getFrameRegister(MF);
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else
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FrameReg = ABI.GetStackPtr();
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} else
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FrameReg = getFrameRegister(MF);
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// Calculate final offset.
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// - There is no need to change the offset if the frame object is one of the
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// following: an outgoing argument, pointer to a dynamically allocated
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// stack space or a $gp restore location,
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// - If the frame object is any of the following, its offset must be adjusted
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// by adding the size of the stack:
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// incoming argument, callee-saved register location or local variable.
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bool IsKill = false;
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int64_t Offset;
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Offset = SPOffset + (int64_t)StackSize;
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Offset += MI.getOperand(OpNo + 1).getImm();
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LLVM_DEBUG(errs() << "Offset : " << Offset << "\n"
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<< "<--------->\n");
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if (!MI.isDebugValue()) {
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// Make sure Offset fits within the field available.
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// For MSA instructions, this is a 10-bit signed immediate (scaled by
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// element size), otherwise it is a 16-bit signed immediate.
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unsigned OffsetBitSize =
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getLoadStoreOffsetSizeInBits(MI.getOpcode(), MI.getOperand(OpNo - 1));
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unsigned OffsetAlign = getLoadStoreOffsetAlign(MI.getOpcode());
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if (OffsetBitSize < 16 && isInt<16>(Offset) &&
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(!isIntN(OffsetBitSize, Offset) ||
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OffsetToAlignment(Offset, OffsetAlign) != 0)) {
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// If we have an offset that needs to fit into a signed n-bit immediate
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// (where n < 16) and doesn't, but does fit into 16-bits then use an ADDiu
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc DL = II->getDebugLoc();
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const TargetRegisterClass *PtrRC =
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ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
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MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
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unsigned Reg = RegInfo.createVirtualRegister(PtrRC);
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const MipsSEInstrInfo &TII =
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*static_cast<const MipsSEInstrInfo *>(
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MBB.getParent()->getSubtarget().getInstrInfo());
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BuildMI(MBB, II, DL, TII.get(ABI.GetPtrAddiuOp()), Reg)
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.addReg(FrameReg)
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.addImm(Offset);
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FrameReg = Reg;
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Offset = 0;
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IsKill = true;
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} else if (!isInt<16>(Offset)) {
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// Otherwise split the offset into 16-bit pieces and add it in multiple
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// instructions.
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc DL = II->getDebugLoc();
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unsigned NewImm = 0;
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const MipsSEInstrInfo &TII =
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*static_cast<const MipsSEInstrInfo *>(
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MBB.getParent()->getSubtarget().getInstrInfo());
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unsigned Reg = TII.loadImmediate(Offset, MBB, II, DL,
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OffsetBitSize == 16 ? &NewImm : nullptr);
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BuildMI(MBB, II, DL, TII.get(ABI.GetPtrAdduOp()), Reg).addReg(FrameReg)
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.addReg(Reg, RegState::Kill);
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FrameReg = Reg;
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Offset = SignExtend64<16>(NewImm);
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IsKill = true;
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}
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}
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MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);
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MI.getOperand(OpNo + 1).ChangeToImmediate(Offset);
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}
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