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671f5b9cbf
Adding the scheduling information for the Browadwell (BDW) CPU target. This patch adds the instruction scheduling information for the Broadwell (BDW) architecture target by adding the file X86SchedBroadwell.td located under the X86 Target. We used the scheduling information retrieved from the Broadwell architects in order to create the file. The scheduling information includes latency, number of micro-Ops and used ports by each BDW instruction. The patch continues the scheduling replacement and insertion effort started with the SandyBridge (SNB) target in r310792, the Haswell (HSW) target in r311879, the SkylakeClient (SKL) target in rL313613 + rL315978 and the SkylakeServer (SKX) in rL315175. Performance fluctuations may be expected due to code alignment effects. Reviewers: zvi, RKSimon, craig.topper Differential Revision: https://reviews.llvm.org/D39054 Change-Id: If6f799e5ff60e1091c8d43b05ea78c53581bae01 llvm-svn: 316492
987 lines
37 KiB
TableGen
987 lines
37 KiB
TableGen
//===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This is a target description file for the Intel i386 architecture, referred
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// to here as the "X86" architecture.
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//
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//===----------------------------------------------------------------------===//
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// Get the target-independent interfaces which we are implementing...
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//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// X86 Subtarget state
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//
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def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
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"64-bit mode (x86_64)">;
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def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true",
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"32-bit mode (80386)">;
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def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true",
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"16-bit mode (i8086)">;
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//===----------------------------------------------------------------------===//
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// X86 Subtarget features
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//===----------------------------------------------------------------------===//
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def FeatureX87 : SubtargetFeature<"x87","HasX87", "true",
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"Enable X87 float instructions">;
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def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true",
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"Enable conditional move instructions">;
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def FeaturePOPCNT : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
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"Support POPCNT instruction">;
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def FeatureFXSR : SubtargetFeature<"fxsr", "HasFXSR", "true",
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"Support fxsave/fxrestore instructions">;
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def FeatureXSAVE : SubtargetFeature<"xsave", "HasXSAVE", "true",
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"Support xsave instructions">;
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def FeatureXSAVEOPT: SubtargetFeature<"xsaveopt", "HasXSAVEOPT", "true",
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"Support xsaveopt instructions">;
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def FeatureXSAVEC : SubtargetFeature<"xsavec", "HasXSAVEC", "true",
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"Support xsavec instructions">;
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def FeatureXSAVES : SubtargetFeature<"xsaves", "HasXSAVES", "true",
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"Support xsaves instructions">;
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def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
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"Enable SSE instructions",
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// SSE codegen depends on cmovs, and all
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// SSE1+ processors support them.
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[FeatureCMOV]>;
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def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
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"Enable SSE2 instructions",
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[FeatureSSE1]>;
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def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
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"Enable SSE3 instructions",
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[FeatureSSE2]>;
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def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
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"Enable SSSE3 instructions",
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[FeatureSSE3]>;
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def FeatureSSE41 : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
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"Enable SSE 4.1 instructions",
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[FeatureSSSE3]>;
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def FeatureSSE42 : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
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"Enable SSE 4.2 instructions",
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[FeatureSSE41]>;
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// The MMX subtarget feature is separate from the rest of the SSE features
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// because it's important (for odd compatibility reasons) to be able to
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// turn it off explicitly while allowing SSE+ to be on.
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def FeatureMMX : SubtargetFeature<"mmx","X863DNowLevel", "MMX",
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"Enable MMX instructions">;
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def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
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"Enable 3DNow! instructions",
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[FeatureMMX]>;
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def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
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"Enable 3DNow! Athlon instructions",
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[Feature3DNow]>;
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// All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
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// feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
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// without disabling 64-bit mode.
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def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true",
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"Support 64-bit instructions",
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[FeatureCMOV]>;
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def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
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"64-bit with cmpxchg16b",
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[Feature64Bit]>;
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def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
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"SHLD instruction is slow">;
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def FeatureSlowPMULLD : SubtargetFeature<"slow-pmulld", "IsPMULLDSlow", "true",
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"PMULLD instruction is slow">;
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// FIXME: This should not apply to CPUs that do not have SSE.
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def FeatureSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16",
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"IsUAMem16Slow", "true",
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"Slow unaligned 16-byte memory access">;
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def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
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"IsUAMem32Slow", "true",
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"Slow unaligned 32-byte memory access">;
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def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true",
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"Support SSE 4a instructions",
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[FeatureSSE3]>;
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def FeatureAVX : SubtargetFeature<"avx", "X86SSELevel", "AVX",
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"Enable AVX instructions",
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[FeatureSSE42]>;
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def FeatureAVX2 : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
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"Enable AVX2 instructions",
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[FeatureAVX]>;
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def FeatureAVX512 : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",
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"Enable AVX-512 instructions",
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[FeatureAVX2]>;
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def FeatureERI : SubtargetFeature<"avx512er", "HasERI", "true",
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"Enable AVX-512 Exponential and Reciprocal Instructions",
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[FeatureAVX512]>;
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def FeatureCDI : SubtargetFeature<"avx512cd", "HasCDI", "true",
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"Enable AVX-512 Conflict Detection Instructions",
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[FeatureAVX512]>;
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def FeatureVPOPCNTDQ : SubtargetFeature<"avx512vpopcntdq", "HasVPOPCNTDQ",
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"true", "Enable AVX-512 Population Count Instructions",
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[FeatureAVX512]>;
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def FeaturePFI : SubtargetFeature<"avx512pf", "HasPFI", "true",
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"Enable AVX-512 PreFetch Instructions",
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[FeatureAVX512]>;
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def FeaturePREFETCHWT1 : SubtargetFeature<"prefetchwt1", "HasPFPREFETCHWT1",
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"true",
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"Prefetch with Intent to Write and T1 Hint">;
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def FeatureDQI : SubtargetFeature<"avx512dq", "HasDQI", "true",
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"Enable AVX-512 Doubleword and Quadword Instructions",
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[FeatureAVX512]>;
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def FeatureBWI : SubtargetFeature<"avx512bw", "HasBWI", "true",
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"Enable AVX-512 Byte and Word Instructions",
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[FeatureAVX512]>;
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def FeatureVLX : SubtargetFeature<"avx512vl", "HasVLX", "true",
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"Enable AVX-512 Vector Length eXtensions",
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[FeatureAVX512]>;
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def FeatureVBMI : SubtargetFeature<"avx512vbmi", "HasVBMI", "true",
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"Enable AVX-512 Vector Byte Manipulation Instructions",
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[FeatureBWI]>;
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def FeatureIFMA : SubtargetFeature<"avx512ifma", "HasIFMA", "true",
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"Enable AVX-512 Integer Fused Multiple-Add",
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[FeatureAVX512]>;
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def FeaturePKU : SubtargetFeature<"pku", "HasPKU", "true",
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"Enable protection keys">;
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def FeaturePCLMUL : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
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"Enable packed carry-less multiplication instructions",
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[FeatureSSE2]>;
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def FeatureFMA : SubtargetFeature<"fma", "HasFMA", "true",
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"Enable three-operand fused multiple-add",
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[FeatureAVX]>;
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def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true",
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"Enable four-operand fused multiple-add",
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[FeatureAVX, FeatureSSE4A]>;
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def FeatureXOP : SubtargetFeature<"xop", "HasXOP", "true",
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"Enable XOP instructions",
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[FeatureFMA4]>;
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def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem",
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"HasSSEUnalignedMem", "true",
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"Allow unaligned memory operands with SSE instructions">;
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def FeatureAES : SubtargetFeature<"aes", "HasAES", "true",
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"Enable AES instructions",
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[FeatureSSE2]>;
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def FeatureTBM : SubtargetFeature<"tbm", "HasTBM", "true",
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"Enable TBM instructions">;
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def FeatureLWP : SubtargetFeature<"lwp", "HasLWP", "true",
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"Enable LWP instructions">;
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def FeatureMOVBE : SubtargetFeature<"movbe", "HasMOVBE", "true",
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"Support MOVBE instruction">;
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def FeatureRDRAND : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
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"Support RDRAND instruction">;
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def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true",
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"Support 16-bit floating point conversion instructions",
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[FeatureAVX]>;
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def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
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"Support FS/GS Base instructions">;
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def FeatureLZCNT : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
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"Support LZCNT instruction">;
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def FeatureBMI : SubtargetFeature<"bmi", "HasBMI", "true",
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"Support BMI instructions">;
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def FeatureBMI2 : SubtargetFeature<"bmi2", "HasBMI2", "true",
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"Support BMI2 instructions">;
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def FeatureRTM : SubtargetFeature<"rtm", "HasRTM", "true",
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"Support RTM instructions">;
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def FeatureADX : SubtargetFeature<"adx", "HasADX", "true",
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"Support ADX instructions">;
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def FeatureSHA : SubtargetFeature<"sha", "HasSHA", "true",
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"Enable SHA instructions",
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[FeatureSSE2]>;
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def FeaturePRFCHW : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
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"Support PRFCHW instructions">;
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def FeatureRDSEED : SubtargetFeature<"rdseed", "HasRDSEED", "true",
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"Support RDSEED instruction">;
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def FeatureLAHFSAHF : SubtargetFeature<"sahf", "HasLAHFSAHF", "true",
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"Support LAHF and SAHF instructions">;
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def FeatureMWAITX : SubtargetFeature<"mwaitx", "HasMWAITX", "true",
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"Enable MONITORX/MWAITX timer functionality">;
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def FeatureCLZERO : SubtargetFeature<"clzero", "HasCLZERO", "true",
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"Enable Cache Line Zero">;
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def FeatureMPX : SubtargetFeature<"mpx", "HasMPX", "true",
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"Support MPX instructions">;
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def FeatureLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
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"Use LEA for adjusting the stack pointer">;
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def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
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"HasSlowDivide32", "true",
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"Use 8-bit divide for positive values less than 256">;
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def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divl",
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"HasSlowDivide64", "true",
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"Use 32-bit divide for positive values less than 2^32">;
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def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
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"PadShortFunctions", "true",
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"Pad short functions">;
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def FeatureSGX : SubtargetFeature<"sgx", "HasSGX", "true",
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"Enable Software Guard Extensions">;
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def FeatureCLFLUSHOPT : SubtargetFeature<"clflushopt", "HasCLFLUSHOPT", "true",
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"Flush A Cache Line Optimized">;
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def FeatureCLWB : SubtargetFeature<"clwb", "HasCLWB", "true",
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"Cache Line Write Back">;
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// On some processors, instructions that implicitly take two memory operands are
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// slow. In practice, this means that CALL, PUSH, and POP with memory operands
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// should be avoided in favor of a MOV + register CALL/PUSH/POP.
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def FeatureSlowTwoMemOps : SubtargetFeature<"slow-two-mem-ops",
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"SlowTwoMemOps", "true",
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"Two memory operand instructions are slow">;
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def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
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"LEA instruction needs inputs at AG stage">;
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def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
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"LEA instruction with certain arguments is slow">;
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def FeatureSlow3OpsLEA : SubtargetFeature<"slow-3ops-lea", "Slow3OpsLEA", "true",
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"LEA instruction with 3 ops or certain registers is slow">;
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def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
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"INC and DEC instructions are slower than ADD and SUB">;
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def FeatureSoftFloat
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: SubtargetFeature<"soft-float", "UseSoftFloat", "true",
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"Use software floating point features.">;
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// On some X86 processors, there is no performance hazard to writing only the
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// lower parts of a YMM or ZMM register without clearing the upper part.
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def FeatureFastPartialYMMorZMMWrite
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: SubtargetFeature<"fast-partial-ymm-or-zmm-write",
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"HasFastPartialYMMorZMMWrite",
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"true", "Partial writes to YMM/ZMM registers are fast">;
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// FeatureFastScalarFSQRT should be enabled if scalar FSQRT has shorter latency
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// than the corresponding NR code. FeatureFastVectorFSQRT should be enabled if
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// vector FSQRT has higher throughput than the corresponding NR code.
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// The idea is that throughput bound code is likely to be vectorized, so for
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// vectorized code we should care about the throughput of SQRT operations.
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// But if the code is scalar that probably means that the code has some kind of
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// dependency and we should care more about reducing the latency.
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def FeatureFastScalarFSQRT
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: SubtargetFeature<"fast-scalar-fsqrt", "HasFastScalarFSQRT",
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"true", "Scalar SQRT is fast (disable Newton-Raphson)">;
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def FeatureFastVectorFSQRT
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: SubtargetFeature<"fast-vector-fsqrt", "HasFastVectorFSQRT",
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"true", "Vector SQRT is fast (disable Newton-Raphson)">;
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// If lzcnt has equivalent latency/throughput to most simple integer ops, it can
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// be used to replace test/set sequences.
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def FeatureFastLZCNT
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: SubtargetFeature<
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"fast-lzcnt", "HasFastLZCNT", "true",
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"LZCNT instructions are as fast as most simple integer ops">;
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// Sandy Bridge and newer processors can use SHLD with the same source on both
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// inputs to implement rotate to avoid the partial flag update of the normal
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// rotate instructions.
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def FeatureFastSHLDRotate
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: SubtargetFeature<
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"fast-shld-rotate", "HasFastSHLDRotate", "true",
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"SHLD can be used as a faster rotate">;
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// Ivy Bridge and newer processors have enhanced REP MOVSB and STOSB (aka
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// "string operations"). See "REP String Enhancement" in the Intel Software
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// Development Manual. This feature essentially means that REP MOVSB will copy
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// using the largest available size instead of copying bytes one by one, making
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// it at least as fast as REPMOVS{W,D,Q}.
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def FeatureERMSB
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: SubtargetFeature<
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"ermsb", "HasERMSB", "true",
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"REP MOVS/STOS are fast">;
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// Sandy Bridge and newer processors have many instructions that can be
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// fused with conditional branches and pass through the CPU as a single
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// operation.
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def FeatureMacroFusion
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: SubtargetFeature<"macrofusion", "HasMacroFusion", "true",
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"Various instructions can be fused with conditional branches">;
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//===----------------------------------------------------------------------===//
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// X86 processors supported.
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//===----------------------------------------------------------------------===//
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include "X86Schedule.td"
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def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
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"Intel Atom processors">;
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def ProcIntelSLM : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM",
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"Intel Silvermont processors">;
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def ProcIntelGLM : SubtargetFeature<"glm", "X86ProcFamily", "IntelGLM",
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"Intel Goldmont processors">;
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def ProcIntelHSW : SubtargetFeature<"haswell", "X86ProcFamily",
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"IntelHaswell", "Intel Haswell processors">;
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def ProcIntelBDW : SubtargetFeature<"broadwell", "X86ProcFamily",
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"IntelBroadwell", "Intel Broadwell processors">;
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def ProcIntelSKL : SubtargetFeature<"skylake", "X86ProcFamily",
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"IntelSkylake", "Intel Skylake processors">;
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def ProcIntelKNL : SubtargetFeature<"knl", "X86ProcFamily",
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"IntelKNL", "Intel Knights Landing processors">;
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def ProcIntelSKX : SubtargetFeature<"skx", "X86ProcFamily",
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"IntelSKX", "Intel Skylake Server processors">;
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def ProcIntelCNL : SubtargetFeature<"cannonlake", "X86ProcFamily",
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"IntelCannonlake", "Intel Cannonlake processors">;
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class Proc<string Name, list<SubtargetFeature> Features>
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: ProcessorModel<Name, GenericModel, Features>;
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def : Proc<"generic", [FeatureX87, FeatureSlowUAMem16]>;
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def : Proc<"i386", [FeatureX87, FeatureSlowUAMem16]>;
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def : Proc<"i486", [FeatureX87, FeatureSlowUAMem16]>;
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def : Proc<"i586", [FeatureX87, FeatureSlowUAMem16]>;
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def : Proc<"pentium", [FeatureX87, FeatureSlowUAMem16]>;
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def : Proc<"pentium-mmx", [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
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def : Proc<"i686", [FeatureX87, FeatureSlowUAMem16]>;
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def : Proc<"pentiumpro", [FeatureX87, FeatureSlowUAMem16, FeatureCMOV]>;
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def : Proc<"pentium2", [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
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FeatureCMOV, FeatureFXSR]>;
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def : Proc<"pentium3", [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
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FeatureSSE1, FeatureFXSR]>;
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def : Proc<"pentium3m", [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
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FeatureSSE1, FeatureFXSR]>;
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// Enable the PostRAScheduler for SSE2 and SSE3 class cpus.
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// The intent is to enable it for pentium4 which is the current default
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// processor in a vanilla 32-bit clang compilation when no specific
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// architecture is specified. This generally gives a nice performance
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// increase on silvermont, with largely neutral behavior on other
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// contemporary large core processors.
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// pentium-m, pentium4m, prescott and nocona are included as a preventative
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// measure to avoid performance surprises, in case clang's default cpu
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// changes slightly.
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def : ProcessorModel<"pentium-m", GenericPostRAModel,
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[FeatureX87, FeatureSlowUAMem16, FeatureMMX,
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FeatureSSE2, FeatureFXSR]>;
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def : ProcessorModel<"pentium4", GenericPostRAModel,
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[FeatureX87, FeatureSlowUAMem16, FeatureMMX,
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FeatureSSE2, FeatureFXSR]>;
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def : ProcessorModel<"pentium4m", GenericPostRAModel,
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[FeatureX87, FeatureSlowUAMem16, FeatureMMX,
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FeatureSSE2, FeatureFXSR]>;
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// Intel Quark.
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def : Proc<"lakemont", []>;
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// Intel Core Duo.
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def : ProcessorModel<"yonah", SandyBridgeModel,
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[FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE3,
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FeatureFXSR]>;
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// NetBurst.
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def : ProcessorModel<"prescott", GenericPostRAModel,
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[FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE3,
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FeatureFXSR]>;
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def : ProcessorModel<"nocona", GenericPostRAModel, [
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FeatureX87,
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FeatureSlowUAMem16,
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FeatureMMX,
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FeatureSSE3,
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FeatureFXSR,
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FeatureCMPXCHG16B
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|
]>;
|
|
|
|
// Intel Core 2 Solo/Duo.
|
|
def : ProcessorModel<"core2", SandyBridgeModel, [
|
|
FeatureX87,
|
|
FeatureSlowUAMem16,
|
|
FeatureMMX,
|
|
FeatureSSSE3,
|
|
FeatureFXSR,
|
|
FeatureCMPXCHG16B,
|
|
FeatureLAHFSAHF,
|
|
FeatureMacroFusion
|
|
]>;
|
|
def : ProcessorModel<"penryn", SandyBridgeModel, [
|
|
FeatureX87,
|
|
FeatureSlowUAMem16,
|
|
FeatureMMX,
|
|
FeatureSSE41,
|
|
FeatureFXSR,
|
|
FeatureCMPXCHG16B,
|
|
FeatureLAHFSAHF,
|
|
FeatureMacroFusion
|
|
]>;
|
|
|
|
// Atom CPUs.
|
|
class BonnellProc<string Name> : ProcessorModel<Name, AtomModel, [
|
|
ProcIntelAtom,
|
|
FeatureX87,
|
|
FeatureSlowUAMem16,
|
|
FeatureMMX,
|
|
FeatureSSSE3,
|
|
FeatureFXSR,
|
|
FeatureCMPXCHG16B,
|
|
FeatureMOVBE,
|
|
FeatureLEAForSP,
|
|
FeatureSlowDivide32,
|
|
FeatureSlowDivide64,
|
|
FeatureSlowTwoMemOps,
|
|
FeatureLEAUsesAG,
|
|
FeaturePadShortFunctions,
|
|
FeatureLAHFSAHF
|
|
]>;
|
|
def : BonnellProc<"bonnell">;
|
|
def : BonnellProc<"atom">; // Pin the generic name to the baseline.
|
|
|
|
class SilvermontProc<string Name> : ProcessorModel<Name, SLMModel, [
|
|
ProcIntelSLM,
|
|
FeatureX87,
|
|
FeatureMMX,
|
|
FeatureSSE42,
|
|
FeatureFXSR,
|
|
FeatureCMPXCHG16B,
|
|
FeatureMOVBE,
|
|
FeaturePOPCNT,
|
|
FeaturePCLMUL,
|
|
FeatureAES,
|
|
FeatureSlowDivide64,
|
|
FeatureSlowTwoMemOps,
|
|
FeaturePRFCHW,
|
|
FeatureSlowLEA,
|
|
FeatureSlowIncDec,
|
|
FeatureSlowPMULLD,
|
|
FeatureLAHFSAHF
|
|
]>;
|
|
def : SilvermontProc<"silvermont">;
|
|
def : SilvermontProc<"slm">; // Legacy alias.
|
|
|
|
class GoldmontProc<string Name> : ProcessorModel<Name, SLMModel, [
|
|
ProcIntelGLM,
|
|
FeatureX87,
|
|
FeatureMMX,
|
|
FeatureSSE42,
|
|
FeatureFXSR,
|
|
FeatureCMPXCHG16B,
|
|
FeatureMOVBE,
|
|
FeaturePOPCNT,
|
|
FeaturePCLMUL,
|
|
FeatureAES,
|
|
FeaturePRFCHW,
|
|
FeatureSlowTwoMemOps,
|
|
FeatureSlowLEA,
|
|
FeatureSlowIncDec,
|
|
FeatureLAHFSAHF,
|
|
FeatureMPX,
|
|
FeatureSHA,
|
|
FeatureRDRAND,
|
|
FeatureRDSEED,
|
|
FeatureXSAVE,
|
|
FeatureXSAVEOPT,
|
|
FeatureXSAVEC,
|
|
FeatureXSAVES,
|
|
FeatureCLFLUSHOPT,
|
|
FeatureFSGSBase
|
|
]>;
|
|
def : GoldmontProc<"goldmont">;
|
|
|
|
// "Arrandale" along with corei3 and corei5
|
|
class NehalemProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
|
|
FeatureX87,
|
|
FeatureMMX,
|
|
FeatureSSE42,
|
|
FeatureFXSR,
|
|
FeatureCMPXCHG16B,
|
|
FeaturePOPCNT,
|
|
FeatureLAHFSAHF,
|
|
FeatureMacroFusion
|
|
]>;
|
|
def : NehalemProc<"nehalem">;
|
|
def : NehalemProc<"corei7">;
|
|
|
|
// Westmere is a similar machine to nehalem with some additional features.
|
|
// Westmere is the corei3/i5/i7 path from nehalem to sandybridge
|
|
class WestmereProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
|
|
FeatureX87,
|
|
FeatureMMX,
|
|
FeatureSSE42,
|
|
FeatureFXSR,
|
|
FeatureCMPXCHG16B,
|
|
FeaturePOPCNT,
|
|
FeatureAES,
|
|
FeaturePCLMUL,
|
|
FeatureLAHFSAHF,
|
|
FeatureMacroFusion
|
|
]>;
|
|
def : WestmereProc<"westmere">;
|
|
|
|
class ProcessorFeatures<list<SubtargetFeature> Inherited,
|
|
list<SubtargetFeature> NewFeatures> {
|
|
list<SubtargetFeature> Value = !listconcat(Inherited, NewFeatures);
|
|
}
|
|
|
|
class ProcModel<string Name, SchedMachineModel Model,
|
|
list<SubtargetFeature> ProcFeatures,
|
|
list<SubtargetFeature> OtherFeatures> :
|
|
ProcessorModel<Name, Model, !listconcat(ProcFeatures, OtherFeatures)>;
|
|
|
|
// SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
|
|
// rather than a superset.
|
|
def SNBFeatures : ProcessorFeatures<[], [
|
|
FeatureX87,
|
|
FeatureMMX,
|
|
FeatureAVX,
|
|
FeatureFXSR,
|
|
FeatureCMPXCHG16B,
|
|
FeaturePOPCNT,
|
|
FeatureAES,
|
|
FeatureSlowDivide64,
|
|
FeaturePCLMUL,
|
|
FeatureXSAVE,
|
|
FeatureXSAVEOPT,
|
|
FeatureLAHFSAHF,
|
|
FeatureSlow3OpsLEA,
|
|
FeatureFastScalarFSQRT,
|
|
FeatureFastSHLDRotate,
|
|
FeatureSlowIncDec,
|
|
FeatureMacroFusion
|
|
]>;
|
|
|
|
class SandyBridgeProc<string Name> : ProcModel<Name, SandyBridgeModel,
|
|
SNBFeatures.Value, [
|
|
FeatureSlowUAMem32
|
|
]>;
|
|
def : SandyBridgeProc<"sandybridge">;
|
|
def : SandyBridgeProc<"corei7-avx">; // Legacy alias.
|
|
|
|
def IVBFeatures : ProcessorFeatures<SNBFeatures.Value, [
|
|
FeatureRDRAND,
|
|
FeatureF16C,
|
|
FeatureFSGSBase
|
|
]>;
|
|
|
|
class IvyBridgeProc<string Name> : ProcModel<Name, SandyBridgeModel,
|
|
IVBFeatures.Value, [
|
|
FeatureSlowUAMem32
|
|
]>;
|
|
def : IvyBridgeProc<"ivybridge">;
|
|
def : IvyBridgeProc<"core-avx-i">; // Legacy alias.
|
|
|
|
def HSWFeatures : ProcessorFeatures<IVBFeatures.Value, [
|
|
FeatureAVX2,
|
|
FeatureBMI,
|
|
FeatureBMI2,
|
|
FeatureERMSB,
|
|
FeatureFMA,
|
|
FeatureLZCNT,
|
|
FeatureMOVBE
|
|
]>;
|
|
|
|
class HaswellProc<string Name> : ProcModel<Name, HaswellModel,
|
|
HSWFeatures.Value, [
|
|
ProcIntelHSW
|
|
]>;
|
|
def : HaswellProc<"haswell">;
|
|
def : HaswellProc<"core-avx2">; // Legacy alias.
|
|
|
|
def BDWFeatures : ProcessorFeatures<HSWFeatures.Value, [
|
|
FeatureADX,
|
|
FeatureRDSEED
|
|
]>;
|
|
class BroadwellProc<string Name> : ProcModel<Name, BroadwellModel,
|
|
BDWFeatures.Value, [
|
|
ProcIntelBDW
|
|
]>;
|
|
def : BroadwellProc<"broadwell">;
|
|
|
|
def SKLFeatures : ProcessorFeatures<BDWFeatures.Value, [
|
|
FeatureMPX,
|
|
FeatureRTM,
|
|
FeatureXSAVEC,
|
|
FeatureXSAVES,
|
|
FeatureSGX,
|
|
FeatureCLFLUSHOPT,
|
|
FeatureFastVectorFSQRT
|
|
]>;
|
|
|
|
class SkylakeClientProc<string Name> : ProcModel<Name, SkylakeClientModel,
|
|
SKLFeatures.Value, [
|
|
ProcIntelSKL
|
|
]>;
|
|
def : SkylakeClientProc<"skylake">;
|
|
|
|
def KNLFeatures : ProcessorFeatures<IVBFeatures.Value, [
|
|
FeatureAVX512,
|
|
FeatureERI,
|
|
FeatureCDI,
|
|
FeaturePFI,
|
|
FeaturePREFETCHWT1,
|
|
FeatureADX,
|
|
FeatureRDSEED,
|
|
FeatureMOVBE,
|
|
FeatureLZCNT,
|
|
FeatureBMI,
|
|
FeatureBMI2,
|
|
FeatureFMA
|
|
]>;
|
|
|
|
// FIXME: define KNL model
|
|
class KnightsLandingProc<string Name> : ProcModel<Name, HaswellModel,
|
|
KNLFeatures.Value, [
|
|
ProcIntelKNL,
|
|
FeatureSlowTwoMemOps,
|
|
FeatureFastPartialYMMorZMMWrite
|
|
]>;
|
|
def : KnightsLandingProc<"knl">;
|
|
|
|
class KnightsMillProc<string Name> : ProcModel<Name, HaswellModel,
|
|
KNLFeatures.Value, [
|
|
ProcIntelKNL,
|
|
FeatureSlowTwoMemOps,
|
|
FeatureFastPartialYMMorZMMWrite
|
|
]>;
|
|
def : KnightsMillProc<"knm">; // TODO Add AVX5124FMAPS/AVX5124VNNIW features
|
|
|
|
def SKXFeatures : ProcessorFeatures<SKLFeatures.Value, [
|
|
FeatureAVX512,
|
|
FeatureCDI,
|
|
FeatureDQI,
|
|
FeatureBWI,
|
|
FeatureVLX,
|
|
FeaturePKU,
|
|
FeatureCLWB
|
|
]>;
|
|
|
|
class SkylakeServerProc<string Name> : ProcModel<Name, SkylakeServerModel,
|
|
SKXFeatures.Value, [
|
|
ProcIntelSKX
|
|
]>;
|
|
def : SkylakeServerProc<"skylake-avx512">;
|
|
def : SkylakeServerProc<"skx">; // Legacy alias.
|
|
|
|
def CNLFeatures : ProcessorFeatures<SKXFeatures.Value, [
|
|
FeatureVBMI,
|
|
FeatureIFMA,
|
|
FeatureSHA
|
|
]>;
|
|
|
|
class CannonlakeProc<string Name> : ProcModel<Name, HaswellModel,
|
|
CNLFeatures.Value, [
|
|
ProcIntelCNL
|
|
]>;
|
|
def : CannonlakeProc<"cannonlake">;
|
|
|
|
// AMD CPUs.
|
|
|
|
def : Proc<"k6", [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
|
|
def : Proc<"k6-2", [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
|
|
def : Proc<"k6-3", [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
|
|
def : Proc<"athlon", [FeatureX87, FeatureSlowUAMem16, Feature3DNowA,
|
|
FeatureSlowSHLD]>;
|
|
def : Proc<"athlon-tbird", [FeatureX87, FeatureSlowUAMem16, Feature3DNowA,
|
|
FeatureSlowSHLD]>;
|
|
def : Proc<"athlon-4", [FeatureX87, FeatureSlowUAMem16, FeatureSSE1,
|
|
Feature3DNowA, FeatureFXSR, FeatureSlowSHLD]>;
|
|
def : Proc<"athlon-xp", [FeatureX87, FeatureSlowUAMem16, FeatureSSE1,
|
|
Feature3DNowA, FeatureFXSR, FeatureSlowSHLD]>;
|
|
def : Proc<"athlon-mp", [FeatureX87, FeatureSlowUAMem16, FeatureSSE1,
|
|
Feature3DNowA, FeatureFXSR, FeatureSlowSHLD]>;
|
|
def : Proc<"k8", [FeatureX87, FeatureSlowUAMem16, FeatureSSE2,
|
|
Feature3DNowA, FeatureFXSR, Feature64Bit,
|
|
FeatureSlowSHLD]>;
|
|
def : Proc<"opteron", [FeatureX87, FeatureSlowUAMem16, FeatureSSE2,
|
|
Feature3DNowA, FeatureFXSR, Feature64Bit,
|
|
FeatureSlowSHLD]>;
|
|
def : Proc<"athlon64", [FeatureX87, FeatureSlowUAMem16, FeatureSSE2,
|
|
Feature3DNowA, FeatureFXSR, Feature64Bit,
|
|
FeatureSlowSHLD]>;
|
|
def : Proc<"athlon-fx", [FeatureX87, FeatureSlowUAMem16, FeatureSSE2,
|
|
Feature3DNowA, FeatureFXSR, Feature64Bit,
|
|
FeatureSlowSHLD]>;
|
|
def : Proc<"k8-sse3", [FeatureX87, FeatureSlowUAMem16, FeatureSSE3,
|
|
Feature3DNowA, FeatureFXSR, FeatureCMPXCHG16B,
|
|
FeatureSlowSHLD]>;
|
|
def : Proc<"opteron-sse3", [FeatureX87, FeatureSlowUAMem16, FeatureSSE3,
|
|
Feature3DNowA, FeatureFXSR, FeatureCMPXCHG16B,
|
|
FeatureSlowSHLD]>;
|
|
def : Proc<"athlon64-sse3", [FeatureX87, FeatureSlowUAMem16, FeatureSSE3,
|
|
Feature3DNowA, FeatureFXSR, FeatureCMPXCHG16B,
|
|
FeatureSlowSHLD]>;
|
|
def : Proc<"amdfam10", [FeatureX87, FeatureSSE4A, Feature3DNowA,
|
|
FeatureFXSR, FeatureCMPXCHG16B, FeatureLZCNT,
|
|
FeaturePOPCNT, FeatureSlowSHLD,
|
|
FeatureLAHFSAHF]>;
|
|
def : Proc<"barcelona", [FeatureX87, FeatureSSE4A, Feature3DNowA,
|
|
FeatureFXSR, FeatureCMPXCHG16B, FeatureLZCNT,
|
|
FeaturePOPCNT, FeatureSlowSHLD,
|
|
FeatureLAHFSAHF]>;
|
|
|
|
// Bobcat
|
|
def : Proc<"btver1", [
|
|
FeatureX87,
|
|
FeatureMMX,
|
|
FeatureSSSE3,
|
|
FeatureSSE4A,
|
|
FeatureFXSR,
|
|
FeatureCMPXCHG16B,
|
|
FeaturePRFCHW,
|
|
FeatureLZCNT,
|
|
FeaturePOPCNT,
|
|
FeatureSlowSHLD,
|
|
FeatureLAHFSAHF
|
|
]>;
|
|
|
|
// Jaguar
|
|
def : ProcessorModel<"btver2", BtVer2Model, [
|
|
FeatureX87,
|
|
FeatureMMX,
|
|
FeatureAVX,
|
|
FeatureFXSR,
|
|
FeatureSSE4A,
|
|
FeatureCMPXCHG16B,
|
|
FeaturePRFCHW,
|
|
FeatureAES,
|
|
FeaturePCLMUL,
|
|
FeatureBMI,
|
|
FeatureF16C,
|
|
FeatureMOVBE,
|
|
FeatureLZCNT,
|
|
FeatureFastLZCNT,
|
|
FeaturePOPCNT,
|
|
FeatureXSAVE,
|
|
FeatureXSAVEOPT,
|
|
FeatureSlowSHLD,
|
|
FeatureLAHFSAHF,
|
|
FeatureFastPartialYMMorZMMWrite
|
|
]>;
|
|
|
|
// Bulldozer
|
|
def : Proc<"bdver1", [
|
|
FeatureX87,
|
|
FeatureXOP,
|
|
FeatureFMA4,
|
|
FeatureCMPXCHG16B,
|
|
FeatureAES,
|
|
FeaturePRFCHW,
|
|
FeaturePCLMUL,
|
|
FeatureMMX,
|
|
FeatureAVX,
|
|
FeatureFXSR,
|
|
FeatureSSE4A,
|
|
FeatureLZCNT,
|
|
FeaturePOPCNT,
|
|
FeatureXSAVE,
|
|
FeatureLWP,
|
|
FeatureSlowSHLD,
|
|
FeatureLAHFSAHF,
|
|
FeatureMacroFusion
|
|
]>;
|
|
// Piledriver
|
|
def : Proc<"bdver2", [
|
|
FeatureX87,
|
|
FeatureXOP,
|
|
FeatureFMA4,
|
|
FeatureCMPXCHG16B,
|
|
FeatureAES,
|
|
FeaturePRFCHW,
|
|
FeaturePCLMUL,
|
|
FeatureMMX,
|
|
FeatureAVX,
|
|
FeatureFXSR,
|
|
FeatureSSE4A,
|
|
FeatureF16C,
|
|
FeatureLZCNT,
|
|
FeaturePOPCNT,
|
|
FeatureXSAVE,
|
|
FeatureBMI,
|
|
FeatureTBM,
|
|
FeatureLWP,
|
|
FeatureFMA,
|
|
FeatureSlowSHLD,
|
|
FeatureLAHFSAHF,
|
|
FeatureMacroFusion
|
|
]>;
|
|
|
|
// Steamroller
|
|
def : Proc<"bdver3", [
|
|
FeatureX87,
|
|
FeatureXOP,
|
|
FeatureFMA4,
|
|
FeatureCMPXCHG16B,
|
|
FeatureAES,
|
|
FeaturePRFCHW,
|
|
FeaturePCLMUL,
|
|
FeatureMMX,
|
|
FeatureAVX,
|
|
FeatureFXSR,
|
|
FeatureSSE4A,
|
|
FeatureF16C,
|
|
FeatureLZCNT,
|
|
FeaturePOPCNT,
|
|
FeatureXSAVE,
|
|
FeatureBMI,
|
|
FeatureTBM,
|
|
FeatureLWP,
|
|
FeatureFMA,
|
|
FeatureXSAVEOPT,
|
|
FeatureSlowSHLD,
|
|
FeatureFSGSBase,
|
|
FeatureLAHFSAHF,
|
|
FeatureMacroFusion
|
|
]>;
|
|
|
|
// Excavator
|
|
def : Proc<"bdver4", [
|
|
FeatureX87,
|
|
FeatureMMX,
|
|
FeatureAVX2,
|
|
FeatureFXSR,
|
|
FeatureXOP,
|
|
FeatureFMA4,
|
|
FeatureCMPXCHG16B,
|
|
FeatureAES,
|
|
FeaturePRFCHW,
|
|
FeaturePCLMUL,
|
|
FeatureF16C,
|
|
FeatureLZCNT,
|
|
FeaturePOPCNT,
|
|
FeatureXSAVE,
|
|
FeatureBMI,
|
|
FeatureBMI2,
|
|
FeatureTBM,
|
|
FeatureLWP,
|
|
FeatureFMA,
|
|
FeatureXSAVEOPT,
|
|
FeatureSlowSHLD,
|
|
FeatureFSGSBase,
|
|
FeatureLAHFSAHF,
|
|
FeatureMWAITX,
|
|
FeatureMacroFusion
|
|
]>;
|
|
|
|
// Znver1
|
|
def: ProcessorModel<"znver1", Znver1Model, [
|
|
FeatureADX,
|
|
FeatureAES,
|
|
FeatureAVX2,
|
|
FeatureBMI,
|
|
FeatureBMI2,
|
|
FeatureCLFLUSHOPT,
|
|
FeatureCLZERO,
|
|
FeatureCMPXCHG16B,
|
|
FeatureF16C,
|
|
FeatureFMA,
|
|
FeatureFSGSBase,
|
|
FeatureFXSR,
|
|
FeatureFastLZCNT,
|
|
FeatureLAHFSAHF,
|
|
FeatureLZCNT,
|
|
FeatureMacroFusion,
|
|
FeatureMMX,
|
|
FeatureMOVBE,
|
|
FeatureMWAITX,
|
|
FeaturePCLMUL,
|
|
FeaturePOPCNT,
|
|
FeaturePRFCHW,
|
|
FeatureRDRAND,
|
|
FeatureRDSEED,
|
|
FeatureSHA,
|
|
FeatureSSE4A,
|
|
FeatureSlowSHLD,
|
|
FeatureX87,
|
|
FeatureXSAVE,
|
|
FeatureXSAVEC,
|
|
FeatureXSAVEOPT,
|
|
FeatureXSAVES]>;
|
|
|
|
def : Proc<"geode", [FeatureX87, FeatureSlowUAMem16, Feature3DNowA]>;
|
|
|
|
def : Proc<"winchip-c6", [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
|
|
def : Proc<"winchip2", [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
|
|
def : Proc<"c3", [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
|
|
def : Proc<"c3-2", [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
|
|
FeatureSSE1, FeatureFXSR]>;
|
|
|
|
// We also provide a generic 64-bit specific x86 processor model which tries to
|
|
// be good for modern chips without enabling instruction set encodings past the
|
|
// basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
|
|
// modern 64-bit x86 chip, and enables features that are generally beneficial.
|
|
//
|
|
// We currently use the Sandy Bridge model as the default scheduling model as
|
|
// we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
|
|
// covers a huge swath of x86 processors. If there are specific scheduling
|
|
// knobs which need to be tuned differently for AMD chips, we might consider
|
|
// forming a common base for them.
|
|
def : ProcessorModel<"x86-64", SandyBridgeModel, [
|
|
FeatureX87,
|
|
FeatureMMX,
|
|
FeatureSSE2,
|
|
FeatureFXSR,
|
|
Feature64Bit,
|
|
FeatureSlow3OpsLEA,
|
|
FeatureSlowIncDec,
|
|
FeatureMacroFusion
|
|
]>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Register File Description
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "X86RegisterInfo.td"
|
|
include "X86RegisterBanks.td"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Instruction Descriptions
|
|
//===----------------------------------------------------------------------===//
|
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include "X86InstrInfo.td"
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def X86InstrInfo : InstrInfo;
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//===----------------------------------------------------------------------===//
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// Calling Conventions
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//===----------------------------------------------------------------------===//
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include "X86CallingConv.td"
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//===----------------------------------------------------------------------===//
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// Assembly Parser
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//===----------------------------------------------------------------------===//
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def ATTAsmParserVariant : AsmParserVariant {
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int Variant = 0;
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// Variant name.
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string Name = "att";
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// Discard comments in assembly strings.
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string CommentDelimiter = "#";
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// Recognize hard coded registers.
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string RegisterPrefix = "%";
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}
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def IntelAsmParserVariant : AsmParserVariant {
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int Variant = 1;
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// Variant name.
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string Name = "intel";
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// Discard comments in assembly strings.
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string CommentDelimiter = ";";
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// Recognize hard coded registers.
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string RegisterPrefix = "";
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}
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//===----------------------------------------------------------------------===//
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// Assembly Printers
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//===----------------------------------------------------------------------===//
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// The X86 target supports two different syntaxes for emitting machine code.
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// This is controlled by the -x86-asm-syntax={att|intel}
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def ATTAsmWriter : AsmWriter {
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string AsmWriterClassName = "ATTInstPrinter";
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int Variant = 0;
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}
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def IntelAsmWriter : AsmWriter {
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string AsmWriterClassName = "IntelInstPrinter";
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int Variant = 1;
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}
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def X86 : Target {
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// Information about the instructions...
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let InstructionSet = X86InstrInfo;
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let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
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let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
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}
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