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224192bde8
This patch makes one change to GOT handling and two changes to N64's relocation model handling. Furthermore, the jumptable encodings have been corrected for static N64. Big GOT handling is now done via a new SDNode MipsGotHi - this node is unconditionally lowered to an lui instruction. The first change to N64's relocation handling is the lifting of the restriction that N64 always uses PIC. Now it is possible to target static environments. The second change adds support for 64 bit symbols and enables them by default. Previously N64 had patterns for sym32 mode only. In this mode all symbols are assumed to have 32 bit addresses. sym32 mode support is selectable with attribute 'sym32'. A follow on patch for clang will add the necessary frontend parameter. This partially resolves PR/23485. Thanks to Brooks Davis for reporting the issue! This version corrects a "Conditional jump or move depends on uninitialised value(s)" error detected by valgrind present in the original commit. Reviewers: dsanders, seanbruno, zoran.jovanovic, vkalintiris Differential Revision: https://reviews.llvm.org/D23652 llvm-svn: 293279
212 lines
10 KiB
LLVM
212 lines
10 KiB
LLVM
; RUN: llc -march=mips -relocation-model=static < %s | FileCheck --check-prefixes=ALL,SYM32,O32,O32BE %s
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; RUN: llc -march=mipsel -relocation-model=static < %s | FileCheck --check-prefixes=ALL,SYM32,O32,O32LE %s
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; RUN-TODO: llc -march=mips64 -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s
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; RUN-TODO: llc -march=mips64el -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s
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; RUN: llc -march=mips64 -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,NEW %s
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; RUN: llc -march=mips64el -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,NEW %s
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; RUN: llc -march=mips64 -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,SYM64,NEW %s
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; RUN: llc -march=mips64el -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,SYM64,NEW %s
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; Test the floating point arguments for all ABI's and byte orders as specified
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; by section 5 of MD00305 (MIPS ABIs Described).
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;
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; N32/N64 are identical in this area so their checks have been combined into
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; the 'NEW' prefix (the N stands for New).
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@bytes = global [11 x i8] zeroinitializer
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@dwords = global [11 x i64] zeroinitializer
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@floats = global [11 x float] zeroinitializer
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@doubles = global [11 x double] zeroinitializer
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define void @double_args(double %a, double %b, double %c, double %d, double %e,
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double %f, double %g, double %h, double %i) nounwind {
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entry:
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%0 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 1
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store volatile double %a, double* %0
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%1 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 2
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store volatile double %b, double* %1
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%2 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 3
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store volatile double %c, double* %2
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%3 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 4
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store volatile double %d, double* %3
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%4 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 5
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store volatile double %e, double* %4
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%5 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 6
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store volatile double %f, double* %5
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%6 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 7
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store volatile double %g, double* %6
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%7 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 8
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store volatile double %h, double* %7
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%8 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 9
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store volatile double %i, double* %8
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ret void
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}
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; ALL-LABEL: double_args:
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; We won't test the way the global address is calculated in this test. This is
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; just to get the register number for the other checks.
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; SYM32-DAG: addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(doubles)
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; SYM64-DAG: daddiu [[R2:\$[0-9]]], ${{[0-9]+}}, %lo(doubles)
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; The first argument is floating point so floating point registers are used.
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; The first argument is the same for O32/N32/N64 but the second argument differs
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; by register
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; ALL-DAG: sdc1 $f12, 8([[R2]])
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; O32-DAG: sdc1 $f14, 16([[R2]])
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; NEW-DAG: sdc1 $f13, 16([[R2]])
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; O32 has run out of argument registers and starts using the stack
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; O32-DAG: ldc1 [[F1:\$f[0-9]+]], 16($sp)
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; O32-DAG: sdc1 [[F1]], 24([[R2]])
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; NEW-DAG: sdc1 $f14, 24([[R2]])
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; O32-DAG: ldc1 [[F1:\$f[0-9]+]], 24($sp)
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; O32-DAG: sdc1 [[F1]], 32([[R2]])
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; NEW-DAG: sdc1 $f15, 32([[R2]])
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; O32-DAG: ldc1 [[F1:\$f[0-9]+]], 32($sp)
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; O32-DAG: sdc1 [[F1]], 40([[R2]])
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; NEW-DAG: sdc1 $f16, 40([[R2]])
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; O32-DAG: ldc1 [[F1:\$f[0-9]+]], 40($sp)
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; O32-DAG: sdc1 [[F1]], 48([[R2]])
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; NEW-DAG: sdc1 $f17, 48([[R2]])
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; O32-DAG: ldc1 [[F1:\$f[0-9]+]], 48($sp)
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; O32-DAG: sdc1 [[F1]], 56([[R2]])
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; NEW-DAG: sdc1 $f18, 56([[R2]])
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; O32-DAG: ldc1 [[F1:\$f[0-9]+]], 56($sp)
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; O32-DAG: sdc1 [[F1]], 64([[R2]])
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; NEW-DAG: sdc1 $f19, 64([[R2]])
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; N32/N64 have run out of registers and start using the stack too
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; O32-DAG: ldc1 [[F1:\$f[0-9]+]], 64($sp)
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; O32-DAG: sdc1 [[F1]], 72([[R2]])
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; NEW-DAG: ldc1 [[F1:\$f[0-9]+]], 0($sp)
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; NEW-DAG: sdc1 [[F1]], 72([[R2]])
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define void @float_args(float %a, float %b, float %c, float %d, float %e,
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float %f, float %g, float %h, float %i) nounwind {
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entry:
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%0 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 1
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store volatile float %a, float* %0
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%1 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 2
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store volatile float %b, float* %1
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%2 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 3
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store volatile float %c, float* %2
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%3 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 4
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store volatile float %d, float* %3
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%4 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 5
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store volatile float %e, float* %4
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%5 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 6
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store volatile float %f, float* %5
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%6 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 7
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store volatile float %g, float* %6
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%7 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 8
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store volatile float %h, float* %7
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%8 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 9
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store volatile float %i, float* %8
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ret void
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}
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; ALL-LABEL: float_args:
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; We won't test the way the global address is calculated in this test. This is
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; just to get the register number for the other checks.
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; SYM32-DAG: addiu [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(floats)
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; SYM64-DAG: daddiu [[R1:\$[0-9]]], ${{[0-9]+}}, %lo(floats)
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; The first argument is floating point so floating point registers are used.
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; The first argument is the same for O32/N32/N64 but the second argument differs
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; by register
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; ALL-DAG: swc1 $f12, 4([[R1]])
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; O32-DAG: swc1 $f14, 8([[R1]])
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; NEW-DAG: swc1 $f13, 8([[R1]])
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; O32 has run out of argument registers and (in theory) starts using the stack
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; I've yet to find a reference in the documentation about this but GCC uses up
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; the remaining two argument slots in the GPR's first. We'll do the same for
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; compatibility.
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; O32-DAG: sw $6, 12([[R1]])
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; NEW-DAG: swc1 $f14, 12([[R1]])
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; O32-DAG: sw $7, 16([[R1]])
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; NEW-DAG: swc1 $f15, 16([[R1]])
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; O32 is definitely out of registers now and switches to the stack.
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; O32-DAG: lwc1 [[F1:\$f[0-9]+]], 16($sp)
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; O32-DAG: swc1 [[F1]], 20([[R1]])
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; NEW-DAG: swc1 $f16, 20([[R1]])
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; O32-DAG: lwc1 [[F1:\$f[0-9]+]], 20($sp)
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; O32-DAG: swc1 [[F1]], 24([[R1]])
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; NEW-DAG: swc1 $f17, 24([[R1]])
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; O32-DAG: lwc1 [[F1:\$f[0-9]+]], 24($sp)
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; O32-DAG: swc1 [[F1]], 28([[R1]])
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; NEW-DAG: swc1 $f18, 28([[R1]])
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; O32-DAG: lwc1 [[F1:\$f[0-9]+]], 28($sp)
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; O32-DAG: swc1 [[F1]], 32([[R1]])
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; NEW-DAG: swc1 $f19, 32([[R1]])
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; N32/N64 have run out of registers and start using the stack too
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; O32-DAG: lwc1 [[F1:\$f[0-9]+]], 32($sp)
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; O32-DAG: swc1 [[F1]], 36([[R1]])
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; NEW-DAG: lwc1 [[F1:\$f[0-9]+]], 0($sp)
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; NEW-DAG: swc1 [[F1]], 36([[R1]])
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define void @double_arg2(i8 %a, double %b) nounwind {
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entry:
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%0 = getelementptr [11 x i8], [11 x i8]* @bytes, i32 0, i32 1
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store volatile i8 %a, i8* %0
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%1 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 1
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store volatile double %b, double* %1
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ret void
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}
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; ALL-LABEL: double_arg2:
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; We won't test the way the global address is calculated in this test. This is
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; just to get the register number for the other checks.
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; SYM32-DAG: addiu [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(bytes)
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; SYM64-DAG: daddiu [[R1:\$[0-9]]], ${{[0-9]+}}, %lo(bytes)
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; SYM32-DAG: addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(doubles)
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; SYM64-DAG: daddiu [[R2:\$[0-9]]], ${{[0-9]+}}, %lo(doubles)
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; The first argument is the same in O32/N32/N64.
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; ALL-DAG: sb $4, 1([[R1]])
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; The first argument isn't floating point so floating point registers are not
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; used in O32, but N32/N64 will still use them.
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; The second slot is insufficiently aligned for double on O32 so it is skipped.
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; Also, double occupies two slots on O32 and only one for N32/N64.
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; O32LE-DAG: mtc1 $6, [[F1:\$f[0-9]*[02468]+]]
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; O32LE-DAG: mtc1 $7, [[F2:\$f[0-9]*[13579]+]]
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; O32BE-DAG: mtc1 $6, [[F2:\$f[0-9]*[13579]+]]
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; O32BE-DAG: mtc1 $7, [[F1:\$f[0-9]*[02468]+]]
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; O32-DAG: sdc1 [[F1]], 8([[R2]])
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; NEW-DAG: sdc1 $f13, 8([[R2]])
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define void @float_arg2(i8 %a, float %b) nounwind {
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entry:
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%0 = getelementptr [11 x i8], [11 x i8]* @bytes, i32 0, i32 1
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store volatile i8 %a, i8* %0
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%1 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 1
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store volatile float %b, float* %1
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ret void
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}
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; ALL-LABEL: float_arg2:
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; We won't test the way the global address is calculated in this test. This is
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; just to get the register number for the other checks.
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; SYM32-DAG: addiu [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(bytes)
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; SYM64-DAG: daddiu [[R1:\$[0-9]]], ${{[0-9]+}}, %lo(bytes)
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; SYM32-DAG: addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(floats)
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; SYM64-DAG: daddiu [[R2:\$[0-9]]], ${{[0-9]+}}, %lo(floats)
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; The first argument is the same in O32/N32/N64.
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; ALL-DAG: sb $4, 1([[R1]])
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; The first argument isn't floating point so floating point registers are not
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; used in O32, but N32/N64 will still use them.
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; MD00305 and GCC disagree on this one. MD00305 says that floats are treated
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; as 8-byte aligned and occupy two slots on O32. GCC is treating them as 4-byte
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; aligned and occupying one slot. We'll use GCC's definition.
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; O32-DAG: sw $5, 4([[R2]])
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; NEW-DAG: swc1 $f13, 4([[R2]])
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