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https://github.com/RPCS3/llvm-mirror.git
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91bb437eb8
As discussed on PR27654, this patch fixes the triples of a lot of aarch64 tests and enables lit tests on windows This will hopefully help stop cases where windows developers break the aarch64 target Differential Revision: https://reviews.llvm.org/D22191 llvm-svn: 275973
154 lines
5.5 KiB
LLVM
154 lines
5.5 KiB
LLVM
; RUN: llc < %s -mtriple=arm64-eabi -mcpu=cyclone | FileCheck %s
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define i32 @qadds(<4 x i32> %b, <4 x i32> %c) nounwind readnone optsize ssp {
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; CHECK-LABEL: qadds:
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; CHECK: sqadd s0, s0, s1
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%vecext = extractelement <4 x i32> %b, i32 0
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%vecext1 = extractelement <4 x i32> %c, i32 0
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%vqadd.i = tail call i32 @llvm.aarch64.neon.sqadd.i32(i32 %vecext, i32 %vecext1) nounwind
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ret i32 %vqadd.i
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}
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define i64 @qaddd(<2 x i64> %b, <2 x i64> %c) nounwind readnone optsize ssp {
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; CHECK-LABEL: qaddd:
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; CHECK: sqadd d0, d0, d1
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%vecext = extractelement <2 x i64> %b, i32 0
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%vecext1 = extractelement <2 x i64> %c, i32 0
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%vqadd.i = tail call i64 @llvm.aarch64.neon.sqadd.i64(i64 %vecext, i64 %vecext1) nounwind
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ret i64 %vqadd.i
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}
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define i32 @uqadds(<4 x i32> %b, <4 x i32> %c) nounwind readnone optsize ssp {
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; CHECK-LABEL: uqadds:
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; CHECK: uqadd s0, s0, s1
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%vecext = extractelement <4 x i32> %b, i32 0
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%vecext1 = extractelement <4 x i32> %c, i32 0
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%vqadd.i = tail call i32 @llvm.aarch64.neon.uqadd.i32(i32 %vecext, i32 %vecext1) nounwind
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ret i32 %vqadd.i
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}
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define i64 @uqaddd(<2 x i64> %b, <2 x i64> %c) nounwind readnone optsize ssp {
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; CHECK-LABEL: uqaddd:
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; CHECK: uqadd d0, d0, d1
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%vecext = extractelement <2 x i64> %b, i32 0
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%vecext1 = extractelement <2 x i64> %c, i32 0
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%vqadd.i = tail call i64 @llvm.aarch64.neon.uqadd.i64(i64 %vecext, i64 %vecext1) nounwind
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ret i64 %vqadd.i
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}
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declare i64 @llvm.aarch64.neon.uqadd.i64(i64, i64) nounwind readnone
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declare i32 @llvm.aarch64.neon.uqadd.i32(i32, i32) nounwind readnone
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declare i64 @llvm.aarch64.neon.sqadd.i64(i64, i64) nounwind readnone
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declare i32 @llvm.aarch64.neon.sqadd.i32(i32, i32) nounwind readnone
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define i32 @qsubs(<4 x i32> %b, <4 x i32> %c) nounwind readnone optsize ssp {
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; CHECK-LABEL: qsubs:
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; CHECK: sqsub s0, s0, s1
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%vecext = extractelement <4 x i32> %b, i32 0
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%vecext1 = extractelement <4 x i32> %c, i32 0
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%vqsub.i = tail call i32 @llvm.aarch64.neon.sqsub.i32(i32 %vecext, i32 %vecext1) nounwind
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ret i32 %vqsub.i
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}
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define i64 @qsubd(<2 x i64> %b, <2 x i64> %c) nounwind readnone optsize ssp {
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; CHECK-LABEL: qsubd:
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; CHECK: sqsub d0, d0, d1
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%vecext = extractelement <2 x i64> %b, i32 0
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%vecext1 = extractelement <2 x i64> %c, i32 0
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%vqsub.i = tail call i64 @llvm.aarch64.neon.sqsub.i64(i64 %vecext, i64 %vecext1) nounwind
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ret i64 %vqsub.i
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}
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define i32 @uqsubs(<4 x i32> %b, <4 x i32> %c) nounwind readnone optsize ssp {
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; CHECK-LABEL: uqsubs:
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; CHECK: uqsub s0, s0, s1
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%vecext = extractelement <4 x i32> %b, i32 0
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%vecext1 = extractelement <4 x i32> %c, i32 0
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%vqsub.i = tail call i32 @llvm.aarch64.neon.uqsub.i32(i32 %vecext, i32 %vecext1) nounwind
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ret i32 %vqsub.i
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}
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define i64 @uqsubd(<2 x i64> %b, <2 x i64> %c) nounwind readnone optsize ssp {
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; CHECK-LABEL: uqsubd:
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; CHECK: uqsub d0, d0, d1
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%vecext = extractelement <2 x i64> %b, i32 0
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%vecext1 = extractelement <2 x i64> %c, i32 0
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%vqsub.i = tail call i64 @llvm.aarch64.neon.uqsub.i64(i64 %vecext, i64 %vecext1) nounwind
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ret i64 %vqsub.i
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}
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declare i64 @llvm.aarch64.neon.uqsub.i64(i64, i64) nounwind readnone
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declare i32 @llvm.aarch64.neon.uqsub.i32(i32, i32) nounwind readnone
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declare i64 @llvm.aarch64.neon.sqsub.i64(i64, i64) nounwind readnone
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declare i32 @llvm.aarch64.neon.sqsub.i32(i32, i32) nounwind readnone
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define i32 @qabss(<4 x i32> %b, <4 x i32> %c) nounwind readnone {
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; CHECK-LABEL: qabss:
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; CHECK: sqabs s0, s0
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; CHECK: ret
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%vecext = extractelement <4 x i32> %b, i32 0
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%vqabs.i = tail call i32 @llvm.aarch64.neon.sqabs.i32(i32 %vecext) nounwind
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ret i32 %vqabs.i
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}
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define i64 @qabsd(<2 x i64> %b, <2 x i64> %c) nounwind readnone {
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; CHECK-LABEL: qabsd:
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; CHECK: sqabs d0, d0
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; CHECK: ret
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%vecext = extractelement <2 x i64> %b, i32 0
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%vqabs.i = tail call i64 @llvm.aarch64.neon.sqabs.i64(i64 %vecext) nounwind
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ret i64 %vqabs.i
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}
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define i32 @qnegs(<4 x i32> %b, <4 x i32> %c) nounwind readnone {
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; CHECK-LABEL: qnegs:
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; CHECK: sqneg s0, s0
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; CHECK: ret
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%vecext = extractelement <4 x i32> %b, i32 0
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%vqneg.i = tail call i32 @llvm.aarch64.neon.sqneg.i32(i32 %vecext) nounwind
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ret i32 %vqneg.i
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}
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define i64 @qnegd(<2 x i64> %b, <2 x i64> %c) nounwind readnone {
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; CHECK-LABEL: qnegd:
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; CHECK: sqneg d0, d0
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; CHECK: ret
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%vecext = extractelement <2 x i64> %b, i32 0
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%vqneg.i = tail call i64 @llvm.aarch64.neon.sqneg.i64(i64 %vecext) nounwind
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ret i64 %vqneg.i
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}
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declare i64 @llvm.aarch64.neon.sqneg.i64(i64) nounwind readnone
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declare i32 @llvm.aarch64.neon.sqneg.i32(i32) nounwind readnone
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declare i64 @llvm.aarch64.neon.sqabs.i64(i64) nounwind readnone
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declare i32 @llvm.aarch64.neon.sqabs.i32(i32) nounwind readnone
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define i32 @vqmovund(<2 x i64> %b) nounwind readnone {
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; CHECK-LABEL: vqmovund:
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; CHECK: sqxtun s0, d0
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%vecext = extractelement <2 x i64> %b, i32 0
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%vqmovun.i = tail call i32 @llvm.aarch64.neon.scalar.sqxtun.i32.i64(i64 %vecext) nounwind
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ret i32 %vqmovun.i
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}
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define i32 @vqmovnd_s(<2 x i64> %b) nounwind readnone {
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; CHECK-LABEL: vqmovnd_s:
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; CHECK: sqxtn s0, d0
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%vecext = extractelement <2 x i64> %b, i32 0
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%vqmovn.i = tail call i32 @llvm.aarch64.neon.scalar.sqxtn.i32.i64(i64 %vecext) nounwind
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ret i32 %vqmovn.i
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}
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define i32 @vqmovnd_u(<2 x i64> %b) nounwind readnone {
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; CHECK-LABEL: vqmovnd_u:
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; CHECK: uqxtn s0, d0
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%vecext = extractelement <2 x i64> %b, i32 0
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%vqmovn.i = tail call i32 @llvm.aarch64.neon.scalar.uqxtn.i32.i64(i64 %vecext) nounwind
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ret i32 %vqmovn.i
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}
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declare i32 @llvm.aarch64.neon.scalar.uqxtn.i32.i64(i64) nounwind readnone
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declare i32 @llvm.aarch64.neon.scalar.sqxtn.i32.i64(i64) nounwind readnone
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declare i32 @llvm.aarch64.neon.scalar.sqxtun.i32.i64(i64) nounwind readnone
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