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06bdbb1aa9
Disable post-ra scheduler for perturbed tests to appease the bots and to preserve the history of the tests. http://reviews.llvm.org/D15652 llvm-svn: 256158
48 lines
1.6 KiB
LLVM
48 lines
1.6 KiB
LLVM
; RUN: llc -disable-post-ra -o - %s | FileCheck %s
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target triple = "arm64--"
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@out = internal global i32 0, align 4
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; Ensure that we transform select(C0, x, select(C1, x, y)) towards
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; select(C0 | C1, x, y) so we can use CMP;CCMP for the implementation.
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; CHECK-LABEL: test0:
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; CHECK: cmp w0, #7
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; CHECK: ccmp w1, #0, #0, ne
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; CHECK: csel w0, w1, w2, gt
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; CHECK: ret
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define i32 @test0(i32 %v0, i32 %v1, i32 %v2) {
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%cmp1 = icmp eq i32 %v0, 7
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%cmp2 = icmp sgt i32 %v1, 0
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%sel0 = select i1 %cmp1, i32 %v1, i32 %v2
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%sel1 = select i1 %cmp2, i32 %v1, i32 %sel0
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ret i32 %sel1
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}
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; Usually we keep select(C0 | C1, x, y) as is on aarch64 to create CMP;CCMP
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; sequences. This case should be transformed to select(C0, select(C1, x, y), y)
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; anyway to get CSE effects.
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; CHECK-LABEL: test1:
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; CHECK-NOT: ccmp
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; CHECK: cmp w0, #7
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; CHECK: adrp x[[OUTNUM:[0-9]+]], out
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; CHECK: csel w[[SEL0NUM:[0-9]+]], w1, w2, eq
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; CHECK: cmp w[[SEL0NUM]], #13
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; CHECK: csel w[[SEL1NUM:[0-9]+]], w1, w2, lo
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; CHECK: cmp w0, #42
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; CHECK: csel w[[SEL2NUM:[0-9]+]], w1, w[[SEL1NUM]], eq
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; CHECK: str w[[SEL1NUM]], [x[[OUTNUM]], :lo12:out]
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; CHECK: str w[[SEL2NUM]], [x[[OUTNUM]], :lo12:out]
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; CHECK: ret
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define void @test1(i32 %bitset, i32 %val0, i32 %val1) {
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%cmp1 = icmp eq i32 %bitset, 7
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%cond = select i1 %cmp1, i32 %val0, i32 %val1
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%cmp5 = icmp ult i32 %cond, 13
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%cond11 = select i1 %cmp5, i32 %val0, i32 %val1
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%cmp3 = icmp eq i32 %bitset, 42
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%or.cond = or i1 %cmp3, %cmp5
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%cond17 = select i1 %or.cond, i32 %val0, i32 %val1
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store volatile i32 %cond11, i32* @out, align 4
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store volatile i32 %cond17, i32* @out, align 4
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ret void
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}
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