mirror of
https://github.com/RPCS3/llvm-mirror.git
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269 lines
7.2 KiB
LLVM
269 lines
7.2 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 -mattr=+avx2 | FileCheck %s
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; CHECK: variable_shl0
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; CHECK: psllvd
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; CHECK: ret
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define <4 x i32> @variable_shl0(<4 x i32> %x, <4 x i32> %y) {
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%k = shl <4 x i32> %x, %y
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ret <4 x i32> %k
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}
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; CHECK: variable_shl1
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; CHECK: psllvd
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; CHECK: ret
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define <8 x i32> @variable_shl1(<8 x i32> %x, <8 x i32> %y) {
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%k = shl <8 x i32> %x, %y
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ret <8 x i32> %k
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}
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; CHECK: variable_shl2
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; CHECK: psllvq
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; CHECK: ret
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define <2 x i64> @variable_shl2(<2 x i64> %x, <2 x i64> %y) {
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%k = shl <2 x i64> %x, %y
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ret <2 x i64> %k
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}
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; CHECK: variable_shl3
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; CHECK: psllvq
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; CHECK: ret
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define <4 x i64> @variable_shl3(<4 x i64> %x, <4 x i64> %y) {
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%k = shl <4 x i64> %x, %y
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ret <4 x i64> %k
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}
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; CHECK: variable_srl0
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; CHECK: psrlvd
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; CHECK: ret
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define <4 x i32> @variable_srl0(<4 x i32> %x, <4 x i32> %y) {
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%k = lshr <4 x i32> %x, %y
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ret <4 x i32> %k
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}
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; CHECK: variable_srl1
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; CHECK: psrlvd
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; CHECK: ret
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define <8 x i32> @variable_srl1(<8 x i32> %x, <8 x i32> %y) {
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%k = lshr <8 x i32> %x, %y
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ret <8 x i32> %k
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}
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; CHECK: variable_srl2
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; CHECK: psrlvq
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; CHECK: ret
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define <2 x i64> @variable_srl2(<2 x i64> %x, <2 x i64> %y) {
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%k = lshr <2 x i64> %x, %y
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ret <2 x i64> %k
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}
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; CHECK: variable_srl3
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; CHECK: psrlvq
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; CHECK: ret
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define <4 x i64> @variable_srl3(<4 x i64> %x, <4 x i64> %y) {
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%k = lshr <4 x i64> %x, %y
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ret <4 x i64> %k
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}
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; CHECK: variable_sra0
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; CHECK: vpsravd
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; CHECK: ret
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define <4 x i32> @variable_sra0(<4 x i32> %x, <4 x i32> %y) {
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%k = ashr <4 x i32> %x, %y
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ret <4 x i32> %k
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}
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; CHECK: variable_sra1
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; CHECK: vpsravd
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; CHECK: ret
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define <8 x i32> @variable_sra1(<8 x i32> %x, <8 x i32> %y) {
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%k = ashr <8 x i32> %x, %y
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ret <8 x i32> %k
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}
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;;; Shift left
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; CHECK: vpslld
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define <8 x i32> @vshift00(<8 x i32> %a) nounwind readnone {
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%s = shl <8 x i32> %a, <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32
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2>
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ret <8 x i32> %s
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}
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; CHECK: vpsllw
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define <16 x i16> @vshift01(<16 x i16> %a) nounwind readnone {
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%s = shl <16 x i16> %a, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
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ret <16 x i16> %s
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}
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; CHECK: vpsllq
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define <4 x i64> @vshift02(<4 x i64> %a) nounwind readnone {
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%s = shl <4 x i64> %a, <i64 2, i64 2, i64 2, i64 2>
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ret <4 x i64> %s
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}
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;;; Logical Shift right
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; CHECK: vpsrld
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define <8 x i32> @vshift03(<8 x i32> %a) nounwind readnone {
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%s = lshr <8 x i32> %a, <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32
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2>
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ret <8 x i32> %s
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}
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; CHECK: vpsrlw
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define <16 x i16> @vshift04(<16 x i16> %a) nounwind readnone {
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%s = lshr <16 x i16> %a, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
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ret <16 x i16> %s
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}
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; CHECK: vpsrlq
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define <4 x i64> @vshift05(<4 x i64> %a) nounwind readnone {
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%s = lshr <4 x i64> %a, <i64 2, i64 2, i64 2, i64 2>
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ret <4 x i64> %s
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}
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;;; Arithmetic Shift right
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; CHECK: vpsrad
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define <8 x i32> @vshift06(<8 x i32> %a) nounwind readnone {
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%s = ashr <8 x i32> %a, <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32
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2>
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ret <8 x i32> %s
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}
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; CHECK: vpsraw
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define <16 x i16> @vshift07(<16 x i16> %a) nounwind readnone {
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%s = ashr <16 x i16> %a, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
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ret <16 x i16> %s
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}
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; CHECK: variable_sra0_load
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; CHECK: vpsravd (%
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; CHECK: ret
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define <4 x i32> @variable_sra0_load(<4 x i32> %x, <4 x i32>* %y) {
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%y1 = load <4 x i32>* %y
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%k = ashr <4 x i32> %x, %y1
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ret <4 x i32> %k
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}
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; CHECK: variable_sra1_load
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; CHECK: vpsravd (%
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; CHECK: ret
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define <8 x i32> @variable_sra1_load(<8 x i32> %x, <8 x i32>* %y) {
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%y1 = load <8 x i32>* %y
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%k = ashr <8 x i32> %x, %y1
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ret <8 x i32> %k
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}
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; CHECK: variable_shl0_load
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; CHECK: vpsllvd (%
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; CHECK: ret
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define <4 x i32> @variable_shl0_load(<4 x i32> %x, <4 x i32>* %y) {
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%y1 = load <4 x i32>* %y
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%k = shl <4 x i32> %x, %y1
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ret <4 x i32> %k
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}
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; CHECK: variable_shl1_load
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; CHECK: vpsllvd (%
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; CHECK: ret
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define <8 x i32> @variable_shl1_load(<8 x i32> %x, <8 x i32>* %y) {
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%y1 = load <8 x i32>* %y
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%k = shl <8 x i32> %x, %y1
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ret <8 x i32> %k
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}
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; CHECK: variable_shl2_load
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; CHECK: vpsllvq (%
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; CHECK: ret
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define <2 x i64> @variable_shl2_load(<2 x i64> %x, <2 x i64>* %y) {
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%y1 = load <2 x i64>* %y
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%k = shl <2 x i64> %x, %y1
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ret <2 x i64> %k
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}
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; CHECK: variable_shl3_load
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; CHECK: vpsllvq (%
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; CHECK: ret
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define <4 x i64> @variable_shl3_load(<4 x i64> %x, <4 x i64>* %y) {
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%y1 = load <4 x i64>* %y
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%k = shl <4 x i64> %x, %y1
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ret <4 x i64> %k
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}
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; CHECK: variable_srl0_load
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; CHECK: vpsrlvd (%
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; CHECK: ret
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define <4 x i32> @variable_srl0_load(<4 x i32> %x, <4 x i32>* %y) {
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%y1 = load <4 x i32>* %y
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%k = lshr <4 x i32> %x, %y1
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ret <4 x i32> %k
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}
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; CHECK: variable_srl1_load
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; CHECK: vpsrlvd (%
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; CHECK: ret
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define <8 x i32> @variable_srl1_load(<8 x i32> %x, <8 x i32>* %y) {
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%y1 = load <8 x i32>* %y
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%k = lshr <8 x i32> %x, %y1
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ret <8 x i32> %k
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}
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; CHECK: variable_srl2_load
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; CHECK: vpsrlvq (%
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; CHECK: ret
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define <2 x i64> @variable_srl2_load(<2 x i64> %x, <2 x i64>* %y) {
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%y1 = load <2 x i64>* %y
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%k = lshr <2 x i64> %x, %y1
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ret <2 x i64> %k
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}
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; CHECK: variable_srl3_load
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; CHECK: vpsrlvq (%
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; CHECK: ret
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define <4 x i64> @variable_srl3_load(<4 x i64> %x, <4 x i64>* %y) {
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%y1 = load <4 x i64>* %y
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%k = lshr <4 x i64> %x, %y1
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ret <4 x i64> %k
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}
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define <32 x i8> @shl9(<32 x i8> %A) nounwind {
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%B = shl <32 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
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ret <32 x i8> %B
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; CHECK: shl9:
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; CHECK: vpsllw $3
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; CHECK: vpand
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; CHECK: ret
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}
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define <32 x i8> @shr9(<32 x i8> %A) nounwind {
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%B = lshr <32 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
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ret <32 x i8> %B
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; CHECK: shr9:
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; CHECK: vpsrlw $3
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; CHECK: vpand
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; CHECK: ret
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}
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define <32 x i8> @sra_v32i8_7(<32 x i8> %A) nounwind {
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%B = ashr <32 x i8> %A, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
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ret <32 x i8> %B
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; CHECK: sra_v32i8_7:
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; CHECK: vpxor
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; CHECK: vpcmpgtb
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; CHECK: ret
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}
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define <32 x i8> @sra_v32i8(<32 x i8> %A) nounwind {
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%B = ashr <32 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
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ret <32 x i8> %B
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; CHECK: sra_v32i8:
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; CHECK: vpsrlw $3
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; CHECK: vpand
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; CHECK: vpxor
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; CHECK: vpsubb
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; CHECK: ret
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}
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; CHECK: _sext_v16i16
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; CHECK: vpsllw
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; CHECK: vpsraw
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; CHECK-NOT: vinsertf128
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define <16 x i16> @sext_v16i16(<16 x i16> %a) nounwind {
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%b = trunc <16 x i16> %a to <16 x i8>
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%c = sext <16 x i8> %b to <16 x i16>
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ret <16 x i16> %c
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}
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; CHECK: _sext_v8i32
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; CHECK: vpslld
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; CHECK: vpsrad
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; CHECK-NOT: vinsertf128
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define <8 x i32> @sext_v8i32(<8 x i32> %a) nounwind {
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%b = trunc <8 x i32> %a to <8 x i16>
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%c = sext <8 x i16> %b to <8 x i32>
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ret <8 x i32> %c
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}
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