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0c823ae0ed
This required light surgery on the assembler and disassembler because the instructions use an uncommon encoding. They are the only two instructions in x86 that use register operands and two immediates. llvm-svn: 157634
57 lines
1.7 KiB
LLVM
57 lines
1.7 KiB
LLVM
; RUN: llc < %s -mtriple=i686-apple-darwin9 -mattr=sse4a | FileCheck %s
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define void @test1(i8* %p, <4 x float> %a) nounwind optsize ssp {
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; CHECK: test1:
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; CHECK: movntss
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tail call void @llvm.x86.sse4a.movnt.ss(i8* %p, <4 x float> %a) nounwind
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ret void
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}
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declare void @llvm.x86.sse4a.movnt.ss(i8*, <4 x float>)
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define void @test2(i8* %p, <2 x double> %a) nounwind optsize ssp {
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; CHECK: test2:
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; CHECK: movntsd
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tail call void @llvm.x86.sse4a.movnt.sd(i8* %p, <2 x double> %a) nounwind
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ret void
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}
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declare void @llvm.x86.sse4a.movnt.sd(i8*, <2 x double>)
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define <2 x i64> @test3(<2 x i64> %x) nounwind uwtable ssp {
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; CHECK: test3:
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; CHECK: extrq
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%1 = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> %x, i8 3, i8 2)
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ret <2 x i64> %1
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}
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declare <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64>, i8, i8) nounwind
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define <2 x i64> @test4(<2 x i64> %x, <2 x i64> %y) nounwind uwtable ssp {
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; CHECK: test4:
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; CHECK: extrq
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%1 = bitcast <2 x i64> %y to <16 x i8>
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%2 = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> %x, <16 x i8> %1) nounwind
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ret <2 x i64> %2
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}
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declare <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64>, <16 x i8>) nounwind
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define <2 x i64> @test5(<2 x i64> %x, <2 x i64> %y) nounwind uwtable ssp {
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; CHECK: test5:
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; CHECK: insertq
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%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %x, <2 x i64> %y, i8 5, i8 6)
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ret <2 x i64> %1
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}
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declare <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64>, <2 x i64>, i8, i8) nounwind
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define <2 x i64> @test6(<2 x i64> %x, <2 x i64> %y) nounwind uwtable ssp {
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; CHECK: test6:
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; CHECK: insertq
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%1 = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> %x, <2 x i64> %y) nounwind
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ret <2 x i64> %1
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}
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declare <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64>, <2 x i64>) nounwind
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