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7e8e679676
when the set bits aren't the same for both args of the xor. This transformation is in the function TargetLowering::SimplifyDemandedBits in the file lib/CodeGen/SelectionDAG/TargetLowering.cpp. I have tested this test using a previous version of llc which the defect and the a version of llc which does not. I got the expected fail and pass, respectively. This test goes with rdar://11195364 and the check in with the fix: svn r154955 llvm-svn: 155156
39 lines
1.6 KiB
LLVM
39 lines
1.6 KiB
LLVM
; RUN: llc -mtriple=i386-apple-darwin9 -fast-isel=false -O0 < %s | FileCheck %s
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; Gather non-machine specific tests for the transformations in
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; CodeGen/SelectionDAG/TargetLowering. Currently, these
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; can't be tested easily by checking the SDNodes that are
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; the data structures that these transformations act on.
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; Therefore, use X86 assembler output to check against.
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; rdar://11195364 A problem with the transformation:
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; If all of the demanded bits on one side are known, and all of the set
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; bits on that side are also known to be set on the other side, turn this
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; into an AND, as we know the bits will be cleared.
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; The known set (one) bits for the arguments %xor1 are not the same, so the
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; transformation should not occur
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define void @foo(i32 %i32In1, i32 %i32In2, i32 %i32In3, i32 %i32In4,
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i32 %i32In5, i32 %i32In6, i32* %i32StarOut, i1 %i1In1,
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i32* %i32SelOut) nounwind {
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%and3 = and i32 %i32In1, 1362779777
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%or2 = or i32 %i32In2, %i32In3
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%and2 = and i32 %or2, 1362779777
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%xor3 = xor i32 %and3, %and2
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; CHECK: shll
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%shl1 = shl i32 %xor3, %i32In4
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%sub1 = sub i32 %or2, %shl1
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%add1 = add i32 %sub1, %i32In5
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%and1 = and i32 %add1, 1
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%xor2 = xor i32 %and1, 1
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%or1 = or i32 %xor2, 364806994 ;0x15BE8352
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; CHECK-NOT: andl $96239955
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%xor1 = xor i32 %or1, 268567040 ;0x10020200
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; force an output so not DCE'd
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store i32 %xor1, i32* %i32StarOut
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; force not fast isel by using a select
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%i32SelVal = select i1 %i1In1, i32 %i32In1, i32 %xor1
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store i32 %i32SelVal, i32* %i32SelOut
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; CHECK: ret
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ret void
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}
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