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c6a3bfadb3
Statistic compile to always be 0 in release build so this compare would always return false. And in the debug builds Statistic are global variables and remember their values across pass runs. So this compare returns true anytime the pass runs after the first time it modifies something. This was found after reviewing all usages of comparison operators on a Statistic object. We had some internal code that did a compare with a statistic that caused a mismatch in output between debug and release builds. So we did an audit out of paranoia. llvm-svn: 302450
108 lines
3.4 KiB
C++
108 lines
3.4 KiB
C++
//===-- ARMOptimizeBarriersPass - two DMBs without a memory access in between,
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//removed one -===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===------------------------------------------------------------------------------------------===//
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#include "ARM.h"
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#include "ARMInstrInfo.h"
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#include "ARMMachineFunctionInfo.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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using namespace llvm;
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#define DEBUG_TYPE "double barriers"
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STATISTIC(NumDMBsRemoved, "Number of DMBs removed");
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namespace {
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class ARMOptimizeBarriersPass : public MachineFunctionPass {
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public:
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static char ID;
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ARMOptimizeBarriersPass() : MachineFunctionPass(ID) {}
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bool runOnMachineFunction(MachineFunction &Fn) override;
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties().set(
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MachineFunctionProperties::Property::NoVRegs);
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}
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StringRef getPassName() const override { return "optimise barriers pass"; }
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};
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char ARMOptimizeBarriersPass::ID = 0;
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}
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// Returns whether the instruction can safely move past a DMB instruction
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// The current implementation allows this iif MI does not have any possible
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// memory access
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static bool CanMovePastDMB(const MachineInstr *MI) {
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return !(MI->mayLoad() ||
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MI->mayStore() ||
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MI->hasUnmodeledSideEffects() ||
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MI->isCall() ||
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MI->isReturn());
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}
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bool ARMOptimizeBarriersPass::runOnMachineFunction(MachineFunction &MF) {
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if (skipFunction(*MF.getFunction()))
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return false;
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// Vector to store the DMBs we will remove after the first iteration
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std::vector<MachineInstr *> ToRemove;
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// DMBType is the Imm value of the first operand. It determines whether it's a
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// DMB ish, dmb sy, dmb osh, etc
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int64_t DMBType = -1;
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// Find a dmb. If we can move it until the next dmb, tag the second one for
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// removal
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for (auto &MBB : MF) {
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// Will be true when we have seen a DMB, and not seen any instruction since
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// that cannot move past a DMB
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bool IsRemovableNextDMB = false;
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for (auto &MI : MBB) {
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if (MI.getOpcode() == ARM::DMB) {
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if (IsRemovableNextDMB) {
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// If the Imm of this DMB is the same as that of the last DMB, we can
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// tag this second DMB for removal
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if (MI.getOperand(0).getImm() == DMBType) {
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ToRemove.push_back(&MI);
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} else {
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// If it has a different DMBType, we cannot remove it, but will scan
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// for the next DMB, recording this DMB's type as last seen DMB type
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DMBType = MI.getOperand(0).getImm();
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}
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} else {
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// After we see a DMB, a next one is removable
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IsRemovableNextDMB = true;
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DMBType = MI.getOperand(0).getImm();
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}
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} else if (!CanMovePastDMB(&MI)) {
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// If we find an instruction unable to pass past a DMB, a next DMB is
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// not removable
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IsRemovableNextDMB = false;
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}
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}
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}
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bool Changed = false;
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// Remove the tagged DMB
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for (auto MI : ToRemove) {
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MI->eraseFromParent();
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++NumDMBsRemoved;
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Changed = true;
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}
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return Changed;
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}
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/// createARMOptimizeBarriersPass - Returns an instance of the remove double
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/// barriers
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/// pass.
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FunctionPass *llvm::createARMOptimizeBarriersPass() {
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return new ARMOptimizeBarriersPass();
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}
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