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a7ed523af9
This was hitting the default instruction constraint code which uses the register classes in the instruction def, which REG_SEQUENCE does not have. Fixes not constraining the register class for AMDGPU fneg/fabs patterns, which would fail when the use was another generic, unconstrained instruction. Another oddity I noticed is that the temporary registers are created with an unnecessary, but incorrect 16-bit LLT but this shouldn't matter. I'm also still unclear why root and sub-instructions have to be handled differently.
82 lines
4.3 KiB
TableGen
82 lines
4.3 KiB
TableGen
// RUN: llvm-tblgen %s -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s
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include "llvm/Target/Target.td"
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include "GlobalISelEmitterCommon.td"
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// Boilerplate code for setting up some registers with subregs.
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class MyReg<string n, list<Register> subregs = []>
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: Register<n> {
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let SubRegs = subregs;
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}
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class MyClass<int size, list<ValueType> types, dag registers>
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: RegisterClass<"Test", types, size, registers> {
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let Size = size;
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}
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def sub0 : SubRegIndex<16>;
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def sub1 : SubRegIndex<16, 16>;
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def S0 : MyReg<"s0">;
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def S1 : MyReg<"s1">;
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def SRegs : MyClass<16, [i16], (sequence "S%u", 0, 1)>;
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let SubRegIndices = [sub0, sub1] in {
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def D0 : MyReg<"d0", [S0, S1]>;
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}
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def DRegs : MyClass<32, [i32], (sequence "D%u", 0, 0)>;
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def SOP : RegisterOperand<SRegs>;
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def DOP : RegisterOperand<DRegs>;
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def SOME_INSN : I<(outs DRegs:$dst), (ins DOP:$src), []>;
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def SUBSOME_INSN : I<(outs SRegs:$dst), (ins SOP:$src), []>;
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// CHECK: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
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// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SEXT,
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// CHECK-NEXT: // MIs[0] dst
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// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
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// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Test::DRegsRegClassID,
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// CHECK-NEXT: // MIs[0] src
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// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
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// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Test::SRegsRegClassID,
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// CHECK-NEXT: // (sext:{ *:[i32] } SOP:{ *:[i16] }:$src) => (REG_SEQUENCE:{ *:[i32] } DRegs:{ *:[i32] }, (SUBSOME_INSN:{ *:[i16] } SOP:{ *:[i16] }:$src), sub0:{ *:[i32] }, (SUBSOME_INSN:{ *:[i16] } SOP:{ *:[i16] }:$src), sub1:{ *:[i32] })
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// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
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// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
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// CHECK-NEXT: GIR_BuildMI, /*InsnID*/2, /*Opcode*/MyTarget::SUBSOME_INSN,
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// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
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// CHECK-NEXT: GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
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// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
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// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/MyTarget::SUBSOME_INSN,
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// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
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// CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
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// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
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// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::REG_SEQUENCE,
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// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
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// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
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// CHECK-NEXT: GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/1,
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// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
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// CHECK-NEXT: GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/2,
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// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
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// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DRegs*/1,
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// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, /*RC SRegs*/0,
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// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, /*RC SRegs*/0,
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def : Pat<(i32 (sext SOP:$src)),
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(REG_SEQUENCE DRegs, (SUBSOME_INSN SOP:$src), sub0,
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(SUBSOME_INSN SOP:$src), sub1)>;
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// CHECK: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ZEXT,
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// CHECK: GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::REG_SEQUENCE,
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// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
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// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
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// CHECK-NEXT: GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/1,
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// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
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// CHECK-NEXT: GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/2,
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// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC DRegs*/1,
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// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC SRegs*/0,
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// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, /*RC SRegs*/0,
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// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::SOME_INSN,
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// Make sure operands are constrained when REG_SEQUENCE isn't the root instruction.
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def : Pat<(i32 (zext SOP:$src)),
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(SOME_INSN (REG_SEQUENCE DRegs, (SUBSOME_INSN SOP:$src), sub0,
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(SUBSOME_INSN SOP:$src), sub1))>;
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