mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-19 11:02:59 +02:00
c2be58dbb0
For best-case performance on Cortex-A57, we should try to use a balanced mix of odd and even D-registers when performing a critical sequence of independent, non-quadword FP/ASIMD floating-point multiply or multiply-accumulate operations.
This pass attempts to detect situations where the register allocation may adversely affect this load balancing and to change the registers used so as to better utilize the CPU.
Ideally we'd just take each multiply or multiply-accumulate in turn and allocate it alternating even or odd registers. However, multiply-accumulates are most efficiently performed in the same functional unit as their accumulation operand. Therefore this pass tries to find maximal sequences ("Chains") of multiply-accumulates linked via their accumulation operand, and assign them all the same "color" (oddness/evenness).
This optimization affects S-register and D-register floating point multiplies and FMADD/FMAs, as well as vector (floating point only) muls and FMADD/FMA. Q register instructions (and 128-bit vector instructions) are not affected.
llvm-svn: 215199
53 lines
1.8 KiB
CMake
53 lines
1.8 KiB
CMake
set(LLVM_TARGET_DEFINITIONS AArch64.td)
|
|
|
|
tablegen(LLVM AArch64GenRegisterInfo.inc -gen-register-info)
|
|
tablegen(LLVM AArch64GenInstrInfo.inc -gen-instr-info)
|
|
tablegen(LLVM AArch64GenMCCodeEmitter.inc -gen-emitter -mc-emitter)
|
|
tablegen(LLVM AArch64GenMCPseudoLowering.inc -gen-pseudo-lowering)
|
|
tablegen(LLVM AArch64GenAsmWriter.inc -gen-asm-writer)
|
|
tablegen(LLVM AArch64GenAsmWriter1.inc -gen-asm-writer -asmwriternum=1)
|
|
tablegen(LLVM AArch64GenAsmMatcher.inc -gen-asm-matcher)
|
|
tablegen(LLVM AArch64GenDAGISel.inc -gen-dag-isel)
|
|
tablegen(LLVM AArch64GenFastISel.inc -gen-fast-isel)
|
|
tablegen(LLVM AArch64GenCallingConv.inc -gen-callingconv)
|
|
tablegen(LLVM AArch64GenSubtargetInfo.inc -gen-subtarget)
|
|
tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler)
|
|
add_public_tablegen_target(AArch64CommonTableGen)
|
|
|
|
add_llvm_target(AArch64CodeGen
|
|
AArch64A57FPLoadBalancing.cpp
|
|
AArch64AddressTypePromotion.cpp
|
|
AArch64AdvSIMDScalarPass.cpp
|
|
AArch64AsmPrinter.cpp
|
|
AArch64BranchRelaxation.cpp
|
|
AArch64CleanupLocalDynamicTLSPass.cpp
|
|
AArch64CollectLOH.cpp
|
|
AArch64ConditionalCompares.cpp
|
|
AArch64DeadRegisterDefinitionsPass.cpp
|
|
AArch64ExpandPseudoInsts.cpp
|
|
AArch64FastISel.cpp
|
|
AArch64FrameLowering.cpp
|
|
AArch64ISelDAGToDAG.cpp
|
|
AArch64ISelLowering.cpp
|
|
AArch64InstrInfo.cpp
|
|
AArch64LoadStoreOptimizer.cpp
|
|
AArch64MCInstLower.cpp
|
|
AArch64PromoteConstant.cpp
|
|
AArch64RegisterInfo.cpp
|
|
AArch64SelectionDAGInfo.cpp
|
|
AArch64StorePairSuppress.cpp
|
|
AArch64Subtarget.cpp
|
|
AArch64TargetMachine.cpp
|
|
AArch64TargetObjectFile.cpp
|
|
AArch64TargetTransformInfo.cpp
|
|
)
|
|
|
|
add_dependencies(LLVMAArch64CodeGen intrinsics_gen)
|
|
|
|
add_subdirectory(TargetInfo)
|
|
add_subdirectory(AsmParser)
|
|
add_subdirectory(Disassembler)
|
|
add_subdirectory(InstPrinter)
|
|
add_subdirectory(MCTargetDesc)
|
|
add_subdirectory(Utils)
|