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b47927165c
In testing, we've found yet another miscompile caused by the new tables. And this one is even less clear how to fix (we could teach it to fold a 16-bit load instead of the 32-bit load it wants, or block folding entirely). Also, the approach to excluding instructions seems increasingly to not scale well. I have left a more detailed analysis on the review log for the original patch (https://reviews.llvm.org/D32684) along with suggested path forward. I will land an additional test case that I wrote which covers the code that was miscompiling (folding into the output of `pextrw`) in a subsequent commit to keep this a pure revert. For each commit reverted here, I've restricted the revert to the non-test code touching the x86 fold table emission until the last commit where I did revert the test updates. This means the *new* test cases added for `insertps` and `xchg` remain untouched (and continue to pass). Reverted commits: r304540: [X86] Don't fold into memory operands into insertps in the ... r304347: [TableGen] Adapt more places to getValueAsString now ... r304163: [X86] Don't fold away the memory operand of an xchg. r304123: Don't capture a temporary std::string in a StringRef. r304122: Resubmit "[X86] Adding new LLVM TableGen backend that ..." Original commit was in r304088, and after a string of fixes was reverted previously in r304121 to fix build bots, and then re-landed in r304122. llvm-svn: 304762
43 lines
964 B
CMake
43 lines
964 B
CMake
set(LLVM_LINK_COMPONENTS Support)
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add_tablegen(llvm-tblgen LLVM
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AsmMatcherEmitter.cpp
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AsmWriterEmitter.cpp
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AsmWriterInst.cpp
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Attributes.cpp
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CallingConvEmitter.cpp
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CodeEmitterGen.cpp
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CodeGenDAGPatterns.cpp
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CodeGenInstruction.cpp
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CodeGenMapTable.cpp
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CodeGenRegisters.cpp
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CodeGenSchedule.cpp
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CodeGenTarget.cpp
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DAGISelEmitter.cpp
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DAGISelMatcherEmitter.cpp
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DAGISelMatcherGen.cpp
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DAGISelMatcherOpt.cpp
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DAGISelMatcher.cpp
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DFAPacketizerEmitter.cpp
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DisassemblerEmitter.cpp
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FastISelEmitter.cpp
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FixedLenDecoderEmitter.cpp
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GlobalISelEmitter.cpp
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InstrInfoEmitter.cpp
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IntrinsicEmitter.cpp
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OptParserEmitter.cpp
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PseudoLoweringEmitter.cpp
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RegisterBankEmitter.cpp
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RegisterInfoEmitter.cpp
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SearchableTableEmitter.cpp
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SubtargetEmitter.cpp
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SubtargetFeatureInfo.cpp
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TableGen.cpp
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Types.cpp
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X86DisassemblerTables.cpp
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X86EVEX2VEXTablesEmitter.cpp
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X86ModRMFilters.cpp
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X86RecognizableInstr.cpp
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CTagsEmitter.cpp
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)
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